3.3.5. Imprecise Error Register

The Imprecise Error Register characteristics are:

Purpose

Records the CCI-400 interfaces that received an error that is not signaled precisely. The appropriate bit is set, with respect to the interface on which the error was received. Bits are set when one or more error responses are detected, and they are reset on a write of 1 to the corresponding bit.

Accessible using only Secure accesses, unless you set the Secure Access Register. See Table 3.4.

Usage constraints

There are no usage constraints.

Configurations

Available in all CCI-400 configurations.

Attributes

Note

If any of the imprecise error indicator bits are set, the nERRORIRQ signal is asserted, active LOW.

Figure 3.5 shows the bit assignments.

Figure 3.5. Imprecise Error Register bit assignments

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Table 3.6 shows the bit assignments.

Table 3.6. Imprecise Error Register bit assignments

Bits

Reset

Access

Function

[31:21]

-

RAZ/WI

Reserved.

[20]

0b0

RW

Imprecise error indicator for slave interface 4.

[19]

0b0

RW

Imprecise error indicator for slave interface 3.

[18]

0b0

RW

Imprecise error indicator for slave interface 2.

[17]

0b0

RW

Imprecise error indicator for slave interface 1.

[16]

0b0

RW

Imprecise error indicator for slave interface 0.

[15:3]

-

RAZ/WI

Reserved.

[2]

0b0

RW

Imprecise error indicator for master interface 2.

[1]

0b0

RW

Imprecise error indicator for master interface 1.

[0]

0b0

RW

Imprecise error indicator for master interface 0:

0b0

No error from the time this bit was last reset.

0b1

An error response has been received, but not signalled precisely.


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