3.4. Address map

The CCI-400 supports 40-bit addressing, with a global address map. This means that each master has the same view of memory. This is split into 16 regions across the 40-bit address. The decode for each region is determined using a number of CCI-400 inputs that are expected to be static, that is, they are sampled only at reset. The inputs are ADDRMAPx[1:0], where x is an integer from 0-15.


If the CCI-400 is configured to support 44-bit DVM transactions, ARADDRSx inputs are 44 bits wide. In this case the CCI-400 still only supports a 40-bit address map and the top address bits are ignored for non-DVM transactions and are not propagated to master interfaces. The CCI master interfaces always have 40-bit address buses.

Figure 3.19 shows the CCI-400 address map.

Figure 3.19. Address map

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Table 3.23 shows the decoder mapping.

Table 3.23. Decoder mapping




M0, expected to be connected to the system.


M1, expected to be connected to a memory controller.


M2, expected to be connected to a memory controller.


M1 and M2, striped across the region. The stripe size is configured using the STRIPING_GRANULE input. Use this option to load-balance between two memory controllers.

The base address for internal CCI-400 registers is defined using a static input, PERIPHBASE[39:15]. The CCI-400 registers are offset by 0x90000 from this base address and occupy an address region of size 64KB.

For example, if PERIPHBASE is 0x0000000, then the register space occupies the following region:

0x0000090000 to 0x000009FFFF.

Accesses within this region, but not to a valid CCI-400 register, generate a DECERR response.


ARM recommends that PERIPHBASE[39:15] occupies the bottom 4GB address space.

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