3.2. Register summary

Table 3.1 shows the registers in offset order from the base memory address, PERIPHBASE[39:15].

Note

The base address for internal CCI-400 registers is defined using a static input, PERIPHBASE[39:15]. The CCI-400 registers are offset by 0x90000 from this base address and occupy an address region of size 64KB.

For example, if PERIPHBASE is 0x0000000, then the register space occupies the region 0x0000090000 to 0x000009FFFF.

Table 3.1. Register summary

Offset

Type

Reset

Width

Function

0x90000

RW

0x0

32

Control Override Register.

0x90004

RW

0x0

32

Speculation Control Register.

0x90008

RW

0x0

32

Secure Access Register.

0x9000C

RO

0x0

32

Status Register.

0x90010

RW

0x0

32

Imprecise Error Register.

0x90100

RW

0x2000

32

Performance Monitor Control Register (PMCR).

0x90FD0 - 0x90FFC

RO

-

32

Component and Peripheral ID Registers.

Slave interface 0 registers

0x91000

RW

0x0

or

0x80000000[a]

32

Snoop Control Register for slave interface 0.

See Snoop Control Registers.

0x91004

RW

0x0

32

Shareable Override Register for slave interface 0.

See Shareable Override Register.

0x91100

RW

0x0

32

Read Channel QoS Value Override Register for slave interface 0.

See Read Channel QoS Value Override Register.

0x91104

RW

0x0

32

Write Channel QoS Value Override slave interface 0.

See Write Channel QoS Value Override Register.

0x9110C

RW

0x0

32

QoS Control Register for slave interface 0.

See QoS Control Register.

0x91110

RW

0x0

32

Max OT Register for slave interface 0.

See Max OT Registers.

0x91130

RW

0x0

32

Regulator Target Register for slave interface 0.

See Regulator Target Registers.

0x91134

RW

0x0

32

QoS Regulator Scale Factor Register for slave interface 0.

See QoS Regulator Scale Factor Registers.

0x91138

RW

0x0

32

QoS Range Register for slave interface 0.

See QoS Range Register.

Slave interface 1 registers

0x92000

RW

0x0

or

0x80000000[b]

32

Snoop Control Register for slave interface 1.

See Snoop Control Registers.

0x92004

RW

0x0

32

Shareable Override Register for slave interface 1.

See Shareable Override Register.

0x92100

RW

0x0

32

Read Channel QoS Value Override Register for slave interface 1.

See Read Channel QoS Value Override Register.

0x92104

RW

0x0

32

Write Channel QoS Value Override slave interface 1.

See Write Channel QoS Value Override Register.

0x9210C

RW

0x0

32

QoS Control Register for slave interface 1.

See QoS Control Register.

0x92110

RW

0x0

32

Max OT Register for slave interface 1.

See Max OT Registers.

0x92130

RW

0x0

32

Regulator Target Register for slave interface 1.

See Regulator Target Registers.

0x92134

RW

0x0

32

QoS Regulator Scale Factor Register for slave interface 1.

See QoS Regulator Scale Factor Registers.

0x92138

RW

0x0

32

QoS Range Register for slave interface 1.

See QoS Range Register.

Slave interface 2 registers

0x93000

RW

0x0

or

0x80000000[c]

32

Snoop Control Register for slave interface 2.

See Snoop Control Registers.

0x93004

RW

0x0

32

Shareable Override Register for slave interface 2.

See Shareable Override Register.

0x93100

RW

0x0

32

Read Channel QoS Value Override Register for slave interface 2.

See Read Channel QoS Value Override Register.

0x93104

RW

0x0

32

Write Channel QoS Value Override slave interface 2.

See Write Channel QoS Value Override Register.

0x9310C

RW

0x0

32

QoS Control Register for slave interface 2.

See QoS Control Register.

0x93110

RW

0x0

32

Max OT Register for slave interface 2.

See Max OT Registers.

0x93130

RW

0x0

32

Regulator Target Register for slave interface 2.

See Regulator Target Registers.

0x93134

RW

0x0

32

QoS Regulator Scale Factor Register for slave interface 2.

See QoS Regulator Scale Factor Registers.

0x93138

RW

0x0

32

QoS Range Register for slave interface 2.

See QoS Range Register.

Slave interface 3 registers

0x94000

RW

0x0

or

0xC0000000[d]

32

Snoop Control Register for slave interface 3.

See Snoop Control Registers.

0x94100

RW

0x0

32

Read Channel QoS Value Override Register for slave interface 3.

See Read Channel QoS Value Override Register.

0x94104

RW

0x0

32

Write Channel QoS Value Override Register for slave interface 3.

See Write Channel QoS Value Override Register.

0x9410C

RW

0x0

32

QoS Control Register for slave interface 3.

See QoS Control Register.

0x94130

RW

0x0

32

Regulator Target Register for slave interface 3.

See Regulator Target Registers.

0x94134

RW

0x0

32

QoS Regulator Scale Factor Register for slave interface 3.

See QoS Regulator Scale Factor Registers.

0x94138

RW

0x0

32

QoS Range Register for slave interface 3.

See QoS Range Register.

Slave interface 4 registers

0x95000

RW

0x0

or

0xC0000000[e]

32

Snoop Control Register for slave interface 4.

See Snoop Control Registers.

0x95100

RW

0x0

32

Read Channel QoS Value Override Register for slave interface 4.

See Read Channel QoS Value Override Register.

0x95104

RW

0x0

32

Write Channel QoS Value Override slave interface 4.

See Write Channel QoS Value Override Register.

0x9510C

RW

0x0

32

QoS Control Register for slave interface 4.

See QoS Control Register.

0x95130

RW

0x0

32

Regulator Target Register for slave interface 4.

See Regulator Target Registers.

0x95134

RW

0x0

32

QoS Regulator Scale Factor Register for slave interface 4.

See QoS Regulator Scale Factor Registers.

0x95138

RW

0x0

32

QoS Range Register for slave interface 4.

See QoS Range Register.

Cycle counter registers

0x99004

RW

0x0

32

Cycle counter register.

See Event and Cycle Count Registers.

0x99008

RW

0x0

32

Count Control Register for cycle counter.

See Counter Control Registers.

0x9900C

RW

0x0

32

Overflow Flag Status Register for cycle counter.

See Overflow Flag Status Register.

Performance counter 0 registers

0x9A000

RW

0x0

32

Event Select Register for performance counter 0.

See Event Select Register.

0x9A004

RW

0x0

32

Event Count Register for performance counter 0.

See Event and Cycle Count Registers.

0x9A008

RW

0x0

32

Counter Control Register for performance counter 0.

See Counter Control Registers.

0x9A00C

RW

0x0

32

Overflow Flag Status Register for performance counter 0.

See Overflow Flag Status Register.

Performance counter 1 registers

0x9B000

RW

0x0

32

Event Select Register for performance counter 1.

See Event Select Register.

0x9B004

RW

0x0

32

Event Count Register for performance counter 1.

See Event and Cycle Count Registers.

0x9B008

RW

0x0

32

Counter Control Register for performance counter 1.

See Counter Control Registers.

0x9B00C

RW

0x0

32

Overflow Flag Status Register for performance counter 1.

See Overflow Flag Status Register.

Performance counter 2 registers

0x9C000

RW

0x0

32

Event Select Register for performance counter 2.

See Event Select Register.

0x9C004

RW

0x0

32

Event Count Register for performance counter 2.

See Event and Cycle Count Registers.

0x9C008

RW

0x0

32

Counter Control Register for performance counter 2.

See Counter Control Registers.

0x9C00C

RW

0x0

32

Overflow Flag Status Register for performance counter 2.

See Overflow Flag Status Register.

Performance counter 3 registers

0x9D000

RW

0x0

32

Event Select Register for performance counter 3. See Event Select Register.

0x9D004

RW

0x0

32

Event Count Register for performance counter 3. See Event and Cycle Count Registers.

0x9D008

RW

0x0

32

Counter Control Register for performance counter 3. See Counter Control Registers.

0x9D00C

RW

0x0

32

Overflow Flag Status Register for performance counter 3. See Overflow Flag Status Register.

0x9E000 - 0x9FFFF

RW

0x0

32

Reserved.

[a] When ACHANNELEN[0] is set.

[b] When ACHANNELEN[1] is set.

[c] When ACHANNELEN[2] is set.

[d] When ACHANNELEN[3] is set.

[e] When ACHANNELEN[4] is set.


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