2.11.1. QoS value

Each CCI-400 slave interface has ARQOS and AWQOS input signals that transport a transaction-based QoS value. This determines the relative priority between transactions on that interface, or between interfaces. The CCI-400 uses the QoS value when it chooses between transaction requests at arbitration points and within queues. Transaction requests with the highest QoS value are prioritized. The CCI-400 uses a Least Recently Granted (LRG) scheme when two or more transactions share the highest value.

QoS values are propagated by CCI-400. If downstream interconnect and slave devices are sensitive to the QoS value, then the service rate is dependent on this value. The NIC-400 Network Interconnect and the DMC-400 Dynamic Memory Controller are both sensitive to QoS value.

Note

Ensure that you balance the relative priorities of all slave interfaces. For example, setting each to the highest QoS value reduces the arbitration to LRG and no advantage is gained from having a QoS value.

You can override the ARQOS and AWQOS input signals from each slave interface by using a programmable register if the relevant static input signal, QOSOVERRIDE[4:0], with one bit for each of slave interfaces 4-0, is HIGH. The QoS override is either based on a programmable value or uses performance feedback to set the value within a programmable range. Transactions that the CCI-400 generates use the same QoS value as the instigating transaction or the override value if QOSOVERRIDE is set.

Note

QOSOVERRIDE only applies to transactions that have a ARQOS or AWQOS value of 0. Therefore, each interface can have a mixture of traffic that is overridden or regulated and other traffic, with non-zero QoS value, that is unaffected. For example, high priority MMU page table requests might be mixed with high-bandwidth media requests that require regulation.

QoS value regulation

CCI-400 regulation mechanisms vary the transaction QoS value depending on latency or bandwidth achieved through that slave interface. You can program target latency or bandwidth and a QoS value range for each regulator. ARM recommends that achievable targets are set so that the regulator uses the minimum QoS value in most cases and only increases the QoS value, up to the programmed maximum, under worst case conditions. The maximum value for each regulator is 0 at reset, so you must program a maximum value before the regulator can be used.

You can control the rate of change of the regulator integrator by using a programmable scale factor. There are two types of QoS value regulation:

  • Regulation based on latency.

  • Regulation based on bandwidth.

Regulation based on latency

In this regulation mode, QoS values change based on measured latency. The value tends to increase if the latency is greater than the target and decrease if the latency is lower than the target.

Regulation based on bandwidth

For bandwidth regulation, the target used for feedback is the period between successive request handshakes, in cycles. The value tends to increase if the period is greater than the target and decrease if the period is lower than the target. If the average number of bytes per request is known, this is equivalent to a bandwidth measure. Shareable transactions in the CCI-400 are 64 bytes in size, so this is usually a good approximation to use.

There are two modes of operation available when you are using this type of regulation:

Normal mode

In this mode the QoS value remains stable when the master is idle, this is equivalent to measuring the average bandwidth only when the master is active. This is the default mode.

Quiesce High mode

In this mode, the QoS value tends to the maximum programmed value when the master is idle, so when it becomes active, the initial transactions have a high QoS value. This mode is suitable for latency sensitive masters because it allows the master to be serviced with high priority while the bandwidth requirement is below that set. If the master starts to exceed its programmed bandwidth, the priority is reduced. You can use this mechanism to ensure that other masters are not excluded when latency sensitive masters take significant bandwidth.

You enable QoS value regulation by setting the appropriate control bits. See QoS Control Register. When you enable QoS value regulation, ARQOS and AWQOS values are driven by those generated by the regulators, if the original transaction has a zero QoS value and the QOSOVERRIDE configuration input is HIGH.

You can program the regulator mode using the QoS Control Registers.

Note

  • Turning QoS value regulation on when QOSOVERRIDE[x] is set LOW for a specific interface has no effect.

  • Transactions that do not transfer data are not counted for QoS value regulation and do not have their QoS value overridden. These transactions are:

    • CleanUnique.

    • MakeUnique.

    • CleanShared.

    • CleanInvalid.

    • MakeInvalid.

    • Evict.

    • Barriers.

    • DVM transactions.

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