1.4. Interfaces

Figure 1.1 shows an example top-level system using a CCI-400 Cache Coherent Interconnect.

Figure 1.1. Example system with a CCI-400

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Slave interfaces S4 and S3 support the ACE protocol for connection to masters such as Cortex-A15 or Cortex-A7 processors. The CCI-400 manages full coherency and data sharing between the processors. The ADB-400, an asynchronous bridge, can optionally be used between components, to integrate multiple power domains or clock domains.

Slave interfaces S0, S1, and S2 support ACE-Lite and DVM signaling for connection to input and output coherent devices such as the ARM Mali-T604 GPU. You can use DVM signaling for attached MMUs such as the MMU-400.

You can use the NIC-400 Network Interconnect to connect other masters and peripherals in the system.

The ACE-Lite master interfaces M2 and M1 are typically connected to a compatible memory controller such as the DMC-400 Dynamic Memory Controller for DDR2, DDR3, and LPDDR2 memory.

ACE-Lite master interface M0 typically connects to the rest of the system, but it can also be used to connect to memory peripherals. You can use QVN between the CCI-400, the DMC-400, and the NIC-400.

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