Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Issue A

Change

Location

Affects

First release.

-

-


Table B.2. Differences between issue A and issue B

Change

Location

Affects

Added a new section on exclusive accesses.

Exclusive accesses

All revisions

Removed the erroneous reference to the TSPEC regulator.

Regulation based on outstanding transactions

All revisions

Changed the Component and Peripheral ID registers table so that the cells are in order of address offset instead of register name.

Table 3.9

All revisions

Updated the revision number in the Peripheral ID2 register.

Table 3.9

r0p1


Table B.3. Differences between issue B and issue C

Change

Location

Affects

Updated the parameter values for maximum ID width on slave interfaces and maximum size of read and write trackers in master interfaces.

Product revisions

r0p2

Changed the configuration of read and write trackers in master interfaces.

Product revisions

r0p2

Added a description for product improvements.

Product revisions

r0p2

Added a note to the Event list section.

PMU event list

All revisions

Updated the revision number in the Peripheral ID2 register.

Table 3.9

r0p2

Added more information to the description of the Shareable Override Register.

Shareable Override Register

All revisions

Added a description of how to calculate the number of outstanding transactions for the MAX OT Registers.

Max OT Registers

All revisions

Changed the bit range of the RRESPSx signal to cover ACE interfaces and ACE-Lite interfaces. For ACE interfaces it is RRESPSx[3:0] and for ACE-Lite interfaces it is RRESPSx[1:0].

Table A.9

All revisions

Changed the bit range of the RRESPMy signal from [3:0] to [1:0] so it becomes RRESPMy[1:0] instead of RRESPMy[3:0].

Table A.18

All revisions


Table B.4. Differences between issue C and issue D

Change

Location

Affects

Note added to QoS value based on latency.

QoS value regulation

All revisions

Regulation based on outstanding transactions moved to new section.

Regulation based on outstanding transactions

All revisions

Repeat the explanation about the PERIPHBASE offset at strategic locations.

Register summary and Table A.2

All revisions

Configurations within Regulator Target Registers updated.

Regulator Target Registers

All revisions

Configurations within QoS Regulator Scale Factor Registers updated.

QoS Regulator Scale Factor Registers

All revisions

Configurations within QoS Range Register updated.

QoS Range Register

All revisions

ACBARSx signal removed from table because it is not used.

Table A.10

All revisions


Table B.5. Differences between issue D and issue E

ChangeLocationAffects
Updated the usage example of the PMU.Using the PMUAll revisions
Clarification of the base address for the memory-mapped registers.About this programmers modelAll revisions
Snoop control register reset values updated.Table 3.1All revisions
Clarification of how to set the event that a counter counts.Table 3.20All revisions

Table B.6. Differences between issue E and issue F

Change

Location

Affects

New support for QoS Virtual Networks (QVN).

r1p0

New options for address width and QVN configuration.

Configurable options

r1p0

Summary of all changes for r1p0.

Product revisions

r1p0

Speculative fetches can be disabled for master or slave interfaces.

Speculative fetch

r1p0

Changed event bus size and event output format.

Performance Monitoring Unit

r1p0

New error reporting for snoop error for WriteLineUnique and WriteUnique.

Error responses

r1p0


Table B.7. Differences between issue F and issue G

Change

Location

Affects

Added two new design-time options to the Configurable Options section.Configurable optionsr1p1
Updated Performance Monitoring Unit section.Performance Monitoring UnitAll revisions
Row in Table 5-bit event codes, sources: master interfaces M0-M2 Number code[4:0] 0x01 Event description updated.

Table 2.3

All revisions

Component and Peripheral ID registers table updated to show latest CCI-400 revision for bits[7:4].

Table 3.9

r1p1

Table B.8. Differences between issue G and issue H

Change

Location

Affects

Additional information added to Snoop connectivity and control section.Snoop connectivity and controlAll revisions
Added a new section.Removing a master from the coherent domainAll revisions
Updated last paragraph. Speculative fetchAll revisions
Updated Introduction.Performance Monitoring UnitAll revisions
Added ACE and ACE-Lite information.DVM messagesAll revisions
Updated section.

Avoidance of Head-of-Line Blocking

All revisions
Updated Peripheral ID2 register revision for bits[7:4] to this version 0x7.Table 3.9r1p2
EVNTARQOSx and EVNTAWQOSx signals corrected to [3:0].Table A.3All revisions

Table B.9. Differences between issue H and issue I

Change

Location

Affects

Added three more bullets to design-time options.Configurable optionsr1p3
Updated Speculative fetch section, second bullet.Speculative fetchr1p0-r1p3
Added register map diagrams.Chapter 3 Programmers Modelr1p3
Updated fifth bullet concerning PV, last sentence.About this programmers modelr1p3
Updated Control Override Register with bit[5].Table 3.2r1p3
Updated Peripheral ID2 register revision for bits[7:4] to this version 0x8.Table 3.9r1p3
Added note under table.Table 3.10All revisions
Removed three bullets from the note because not they were not relevant to the register.Shareable Override RegisterAll revisions
  • Bit[31] updated to support QoS regulation.

  • Bit[1] updated in diagram and function description of table.

Figure 3.11

Table 3.14

r1p3
  • Bit field [7:5] corrected from [7:0].

  • Added note beneath table for clarification.

Table 3.20

r1p0-r1p3

Updated 0b11 Decode comment in Decoder mapping table.Table 3.23r1p3
STRIPING_GRANULE[2:0] signal added to Configuration signals.Table A.2r1p3
Updated and renamed former Power control signals, C-channel section to AXI low-power interface signals.Table A.19r1p3
Added ACTIVEMy signal section, that used to be part of the Power control signals, C-channel section.Table A.20r1p3

Table B.10. Differences between issue I and issue J

Change

Location

Affects

Updated About the CoreLink Cache Coherent Interconnect section.About the CoreLink Cache Coherent InterconnectAll revisions
Updated Configurable options section with a new bullet on the exclusion of internal logic for unused slave and master interfaces.Configurable optionsr1p4
Updated Product revisions section.Product revisionsr1p4
Added a note under the table.Table 2.4All revisions
Added a table showing the number of slots reserved for high and medium traffic on master interfaces.Table 2.6All revisions
Updated Peripheral ID2 register revision for bits[7:4] to this version 0x9.Table 3.9r1p4
Added ACSRCSx[2:0] signal[a].Table A.10r1p4
Updated AXI low-power interfaces table.Table A.19All revisions

[a] Where x is 0-4


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