ARM CoreLink CCI-400 Cache Coherent Interconnect Technical Reference Manual: 2.4.1. PMU event list

2.4.1. PMU event list

In the context of counting in one of the event counters, each event has an 8-bit identifier, made up as {source,number}. Each source is allocated a 3-bit code that indicates the interface that generated it. Table 2.1 shows the 3-bit source code for events.

Table 2.1. 3-bit source code for events

Code[7:5]	Source
`0x0`	Slave interface 0, S0
`0x1`	Slave interface 1, S1
`0x2`	Slave interface 2, S2
`0x3`	Slave interface 3, S3
`0x4`	Slave interface 4, S4
`0x5`	Master interface 0, M0
`0x6`	Master interface 1, M1
`0x7`	Master interface 2, M2

Table 2.2 shows each event, with its number and bit offset in the EVNTBUS output.

By default, only events relating to Non-secure transactions are recorded. However, if the SPNIDEN input is HIGH, then both Secure and Non-secure events are counted and exported.

Note

Master interface events 0x2 and 0x09-0x10 have no security indicator, so they are counted irrespective of the SPNIDEN input.

Table 2.2 and Table 2.3 show the 5-bit event code event list.

Table 2.2. 5-bit event codes, sources: slave interfaces S0-S4

Event	Number code[4:0]	EVNTBUS offset
Read request handshake: any.	`0x00`	0
Read request handshake: device transaction.	`0x01`	1
Read request handshake: normal, non-shareable or system-shareable, but not barrier or cache maintenance operation.	`0x02`	2
Read request handshake: inner- or outer-shareable, but not barrier, DVM message or cache maintenance operation.	`0x03`	3
Read request handshake: cache maintenance operation.	`0x04`	4
Read request handshake: memory barrier.	`0x05`	5
Read request handshake: synchronization barrier.	`0x06`	6
Read request handshake: DVM message, not synchronization.	`0x07`	7
Read request handshake: DVM message, synchronization.	`0x08`	8
Read request stall cycle because the transaction tracker is full. Increase `SIx_R_MAX` to avoid this stall.	`0x09`	9
Read data last handshake: data returned from the snoop instead of from downstream.	`0x0A`	10
Read data stall cycle: RVALIDS is HIGH, RREADYS is LOW.	`0x0B`	11
Write request handshake: any.	`0x0C`	12
Write request handshake: device transaction.	`0x0D`	13
Write request handshake: normal, non-shareable, or system-shareable, but not barrier.	`0x0E`	14
Write request handshake: inner- or outer-shareable, `WriteBack` or `WriteClean`.	`0x0F`	15
Write request handshake: `WriteUnique`.	`0x10`	16
Write request handshake: `WriteLineUnique`.	`0x11`	17
Write request handshake: `Evict`.	`0x12`	18
Write request stall cycle because the transaction tracker is full. Increase `SIx_W_MAX` to avoid this stall.	`0x13`	19
Read request stall cycle because of a slave interface ID hazard.	`0x14`	20

Table 2.3 shows the 5-bit event code event list.

Table 2.3. 5-bit event codes, sources: master interfaces M0-M2

Event	Number code[4:0]	EVNTBUS offset
RETRY of speculative fetch transaction.^[a]	`0x00`	0
Stall cycle because of an address hazard. A read or write invalidation is stalled because of an outstanding transaction to an overlapping address.	`0x01`	1
Read request stall cycle because of a master interface ID hazard.	`0x02`	2
A read request with a QoS value in the high priority group is stalled for a cycle because the read transaction queue is full. Increase `MIx_R_MAX` to avoid this stall.	`0x03`	3
Read request stall cycle because of a barrier hazard.	`0x04`	4
Write request stall cycle because of a barrier hazard.	`0x05`	5
A write request is stalled for a cycle because the write transaction tracker is full. Increase `MIx_W_MAX` to avoid this stall.	`0x06`	6
A read request with a QoS value in the low priority group is stalled for a cycle because there are no slots available in the read queue for the low priority group.	`0x07`	7
A read request with a QoS value in the medium priority group is stalled for a cycle because there are no slots available in the read queue for the medium priority group.	`0x08`	8
A read request is stalled for a cycle while it was waiting for a QVN token on VN0.	`0x09`	9
A read request is stalled for a cycle while it was waiting for a QVN token on VN1.	`0x0A`	10
A read request is stalled for a cycle while it was waiting for a QVN token on VN2.	`0x0B`	11
A read request is stalled for a cycle while it was waiting for a QVN token on VN3.	`0x0C`	12
A write request is stalled for a cycle while it was waiting for a QVN token on VN0.	`0x0D`	13
A write request is stalled for a cycle while it was waiting for a QVN token on VN1.	`0x0E`	14
A write request is stalled for a cycle while it was waiting for a QVN token on VN2.	`0x0F`	15
A write request is stalled for a cycle while it was waiting for a QVN token on VN3.	`0x10`	16
A `WriteUnique` or `WriteLineUnique` request is stalled for a cycle because of an address hazard.	`0x11`	17
^[a]This event fires when retries are scheduled. If two retries are scheduled simultaneously, only one event is generated.

Event bus

The CCI-400 exports a vector of event signals, EVNTBUS, with the bit allocation that Table 2.4 shows. When an event is triggered, the relevant bit of EVNTBUS is set to HIGH for one clock period.

Table 2.4. EVNTBUS bit allocation

Bits	Source
[158:141]	AMI2 event bus.
[140:123]	AMI1 event bus.
[122:105]	AMI0 event bus.
[104:84]	ASI4 event bus.
[83:63]	ASI3 event bus.
[62:42]	ASI2 event bus.
[41:21]	ASI1 event bus.
[20:0]	ASI0 event bus.

Table 2.2 shows the bit positions that the ASI events have within each group of signals on the event bus.

Note

The width and bit positions in the EVNTBUS output are invariant with the number of CCI-400 interfaces used.

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