1.8. Product revisions

This section describes differences in functionality between product revisions:

r0p0

First release.

r0p0-r0p1

The following changes have been made to this release:

r0p1-r0p2

The following changes have been made to this release:

  • Configuration improvements for the following:

    • Maximum ID width on slave interfaces increased from 8 to 28.

    • Maximum size of read and write trackers in master interfaces increased from 32 to 128.

    • Read and write trackers in master interfaces is now configurable in steps of 1 rather than 2n.

    Improvements for the following:

    • Master interface read tracker slot re-use time to reduce stalls.

    • Slave interface PMU events redefined to improve the counting of device and non-cacheable transactions.

  • Peripheral ID2 register value is changed to reflect the product status:

    Offset

    0xFE8

    Bits

    [7:4]

    Value

    0x2

    For the current version, see the Component and Peripheral ID Registers.

r0p2-r0p3

The following changes have been made to this release:

  • The CCI-400 now supports up to four exclusive access threads from each ACE master and has separate monitors for Secure and Non-secure transactions. See Exclusive accesses.

  • Peripheral ID2 register value is changed to reflect the product status:

    Offset

    0xFE8

    Bits

    [7:4]

    Value

    0x3

    For the current version, see the Component and Peripheral ID Registers.

r0p3-r0p4

The following changes have been made to this release:

  • No functional changes.

  • Peripheral ID2 register value is changed to reflect the product status:

    Offset

    0xFE8

    Bits

    [7:4]

    Value

    0x4

    For the current version, see the Component and Peripheral ID Registers.

r0p4-r1p0

A major upgrade with new or improved functionality. The following changes have been made to this release:

  • Performance improvements:

    • Increased bandwidth for WriteUnique and WriteLineUnique transactions.

    • Improvements to performance when using heterogeneous processor clusters.

    • Reduced read latency.

    • Improved performance with hazards. An ID or address hazard no longer blocks the master interface.

    • Improved performance when a master reuses IDs. A stalled transaction is released earlier.

    • Optimizations in barrier performance.

    • Exclusive access monitor for each processor rather than for each cluster. This improves performance for shareable exclusive transactions.

  • QoS improvements:

    • Support for QVN.

    • QoS value bandwidth regulation in addition to the existing latency regulation.

    • Reservation for read queue slot.

    • Avoidance of head-of-line blocking using priority promotion.

    • Improved visibility of QoS regulator values.

    See also Quality of Service.

  • Additional functionality:

    • WID output on master interfaces helps to connect to AXI3 slaves.

    • Speculative fetches can be disabled for each slave interface and also for each master interface.

    • Configurable option for 44-bit DVM messages.

    • Additional PMU events to support new functionality.

  • Peripheral ID2 register value is changed to reflect the product status:

    Offset

    0xFE8

    Bits

    [7:4]

    Value

    0x5

    For the current version, see the Component and Peripheral ID Registers.

r1p0-r1p1

The following configuration improvements have been made to this release:

  • Frequency improvement at the expense of one cycle of latency on read transactions.

  • Added configurability of WriteUnique and WriteLineUnique tracker sizes.

  • New write ordering configuration options.

  • Option to remove QVN logic when it is not required.

  • Peripheral ID2 register value is changed to reflect the product status:

    Offset

    0xFE8

    Bits

    [7:4]

    Value

    0x6

    For the current version, see the Component and Peripheral ID Registers.

r1p1-r1p2

The following changes have been made to this release:

  • No functional changes.

  • Peripheral ID2 register value is changed to reflect the product status:

    Offset

    0xFE8

    Bits

    [7:4]

    Value

    0x7

    For the current version, see the Component and Peripheral ID Registers.

r1p2-r1p3

The following changes have been made to this release:

  • New options to control region size when using a striped address map.

  • Logic optimizations to improve implementation frequency.

  • New parameters to remove logic for barrier support and QoS regulation if these features are unused.

  • Peripheral ID2 register value is changed to reflect the product status:

    Offset

    0xFE8

    Bits

    [7:4]

    Value

    0x8

    For the current version, see the Component and Peripheral ID Registers.

r1p3-r1p4

The following changes have been made to this release:

  • New output on ACE interfaces: ACSRCSx.

    Where x is 0-4.

  • New parameters to remove logic for unused slave and master interfaces.

  • Peripheral ID2 register value is changed to reflect the product status:

    Offset

    0xFE8

    Bits

    [7:4]

    Value

    0x9

    For the current version, see the Component and Peripheral ID Registers.

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