2.6.1. Imprecise errors

Table 2.5 shows the errors that are signalled as imprecise. All other sources of error are signalled precisely.

Note

An error is signalled either precisely or imprecisely, but never both.

Table 2.5. Imprecise errors

Transaction causing error

Channel receiving error

Imprecise error indicator from

A ReadX snoop that misses in the cache and fetches data from downstream

CR

Slave interface receiving the CR response

Distributed Virtual Memory message

CR

Slave interface receiving the CR response

Speculative fetch that returns an error, but the snoop returns data

R

Master interface receiving the R response

Speculative fetch that must be retried

RMaster interface receiving the R response

Write that the CCI-400 generated

B

Master interface receiving the B response

Snoop error generated by a WriteLineUnique or WriteUnique transaction

CR

Master interface receiving the CR response

Write error for WriteUnique transactions that have been split but not the last transaction in the split sequence

B

Slave interface that received the transaction that was split


The CCI-400 generates a precise DECERR response in the case of a security violation on a CCI-400 register access. See Imprecise Error Register and Security.

Copyright © 2011-2014 ARM. All rights reserved.ARM DDI 0470J
Non-ConfidentialID031714