ARM® CoreLink™ CCI-400 Cache Coherent Interconnect Technical Reference Manual

Revision: r1p5


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the CoreLink Cache Coherent Interconnect
1.2. Compliance
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.6. Test features
1.7. Product documentation, design flow, and architecture
1.7.1. Documentation
1.7.2. Design flow
1.8. Product revisions
2. Functional Description
2.1. About the functions
2.2. Snoop connectivity and control
2.2.1. Removing a master from the coherent domain
2.3. Speculative fetch
2.4. Performance Monitoring Unit
2.4.1. PMU event list
2.4.2. PMU registers
2.4.3. Using the PMU
2.5. Security
2.5.1. Internal programmers view
2.5.2. Non-TrustZone aware masters made secure
2.5.3. Security of master interfaces
2.5.4. Security and the PMU
2.6. Error responses
2.6.1. Imprecise errors
2.7. Cache maintenance operations
2.8. WriteEvict Transactions memory update operation
2.8.1. WriteEvict Transactions
2.9. Barriers
2.10. Exclusive accesses
2.11. DVM messages
2.12. Quality of Service
2.12.1. QoS value
2.12.2. Regulation based on outstanding transactions
2.12.3. QoS programmable registers
2.12.4. QoS Virtual Networks (QVN)
2.13. Clock and reset
2.13.1. Clocking
2.13.2. Reset
3. Programmers Model
3.1. About this programmers model
3.2. Register summary
3.3. Register descriptions
3.3.1. Control Override Register
3.3.2. Speculation Control Register
3.3.3. Secure Access Register
3.3.4. Status Register
3.3.5. Imprecise Error Register
3.3.6. Performance Monitor Control Register (PMCR)
3.3.7. Component and Peripheral ID Registers
3.3.8. Snoop Control Registers
3.3.9. Shareable Override Register
3.3.10. Read Channel QoS Value Override Register
3.3.11. Write Channel QoS Value Override Register
3.3.12. QoS Control Register
3.3.13. Max OT Registers
3.3.14. Regulator Target Registers
3.3.15. QoS Regulator Scale Factor Registers
3.3.16. QoS Range Register
3.3.17. Event Select Register
3.3.18. Event and Cycle Count Registers
3.3.19. Counter Control Registers
3.3.20. Overflow Flag Status Register
3.4. Address map
A. Signal Descriptions
A.1. Signal descriptions
A.1.1. Clock and reset signals
A.1.2. Configuration signals
A.1.3. Debug signals
A.1.4. DFT signal
A.1.5. Slave interface signals
A.1.6. Master interface signals
A.2. Miscellaneous signals
B. Revisions

List of Tables

1. Typographical conventions
2.1. 3-bit source code for events
2.2. 5-bit event codes, sources: slave interfaces S0-S4
2.3. 5-bit event codes, sources: master interfaces M0-M2
2.4. EVNTBUS bit allocation
2.5. Imprecise errors
2.6. Slots reserved for high and medium priority traffic in each master interface
3.1. Register summary
3.2. Control Override Register bit assignments
3.3. Speculation Control Register bit assignments
3.4. Secure Access Register bit assignments
3.5. Status Register bit assignments
3.6. Imprecise Error Register bit assignments
3.7. Performance Monitor Control Register bit assignments
3.8. Relationship between non-invasive debug enable input, NIDEN, and PMCR register settings
3.9. Component and Peripheral ID registers bit assignments
3.10. Snoop Control Registers bit assignments
3.11. Shareable Override Register bit assignments
3.12. Read Channel QoS Value Override Register bit assignments
3.13. Write Channel QoS Value Override Register bit assignments
3.14. QoS Control Register bit assignments
3.15. Max OT Register bit assignments
3.16. Regulator Target Register bit assignments
3.17. QoS Regulator Scale Factor Register bit assignments
3.18. Mapping of Scale Factor Register value to Regulator scale factor
3.19. QoS Range Register bit assignments
3.20. Event Select Register bit assignments
3.21. Counter Control Register bit assignments
3.22. Overflow Flag Status Register bit assignments
3.23. Decoder mapping
A.1. Clock and reset signals
A.2. Configuration signals
A.3. Debug signals
A.4. DFT signal
A.5. Write address channel signals
A.6. Write data channel signals
A.7. Write data response channel signals
A.8. Read address channel signals
A.9. Read data channel signals
A.10. Coherency address channel signals
A.11. Coherency response channel signals
A.12. Coherency data channel signals, full ACE interfaces, S3 and S4 only
A.13. Acknowledge signals, full ACE interfaces, S3 and S4 only
A.14. Write address channel signals
A.15. Write data channel signals
A.16. Write data response channel signals
A.17. Read address channel signals
A.18. Read data channel signals
A.19. AXI low-power interface signals
A.20. ACTIVEMy signal
A.21. QVN signals
A.22. Miscellaneous signals
B.1. Issue A
B.2. Differences between issue A and issue B
B.3. Differences between issue B and issue C
B.4. Differences between issue C and issue D
B.5. Differences between issue D and issue E
B.6. Differences between issue E and issue F
B.7. Differences between issue F and issue G
B.8. Differences between issue G and issue H
B.9. Differences between issue H and issue I
B.10. Differences between issue I and issue J
B.11. Differences between issue J and issue K

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Revision History
Revision A16 May 2011First release for r0p0.
Revision B07 July 2011First release for r0p1.
Revision C16 September 2011First release for r0p2.
Revision D12 March 2012First release for r0p3.
Revision E13 September 2012First release for r0p4.
Revision F25 September 2012First release for r1p0.
Revision G16 November 2012First release for r1p1.
Revision H18 June 2013First release for r1p2.
Revision I12 September 2013First release for r1p3.
Revision J17 March 2014First release for r1p4.
Revision K10 December 2015First release for r1p5.
Copyright © 2011-2015 ARM Limited or its affiliates. All rights reserved.ARM DDI 0470K
Non-ConfidentialID011116