CoreLink GIC-400 Generic Interrupt Controller Technical Reference ManualRevision: r0p1
Home > Signal Descriptions > Interrupt signals

A.3. Interrupt signals

Table A.3 shows the interrupt signals in the GIC-400.

Table A.3. Interrupt controller signals

Signal[a]

Direction

Type

Description[b]

IRQS[NUM_SPIS- 1:0]

Input

Interrupt source

SPIs

nLEGACYIRQ[NUM_CPUS- 1:0]

Input

Interrupt source

PPI with interrupt ID 31

Legacy IRQ signal

nCNTPNSIRQ[NUM_CPUS- 1:0]

Input

Interrupt source

PPI with interrupt ID 30

Non-secure Physical Timer Event

nCNTPSIRQ[NUM_CPUS- 1:0]

Input

Interrupt source

PPI with interrupt ID 29

Secure Physical Timer Event

nLEGACYFIQ[NUM_CPUS- 1:0]

Input

Interrupt source

PPI with interrupt ID 28

Legacy FIQ signal

nCNTVIRQ[NUM_CPUS- 1:0]

Input

Interrupt source

PPI with interrupt ID 27

Virtual Timer Event

nCNTHPIRQ[NUM_CPUS- 1:0]

Input

Interrupt source

PPI with interrupt ID 26

Hypervisor Timer Event

nFIQCPU[NUM_CPUS- 1:0]

Output

Interrupt controller

Non-virtual FIQ to processors

nIRQCPU[NUM_CPUS- 1:0]

Output

Interrupt controller

Non-virtual IRQ to processors

nVFIQCPU[NUM_CPUS- 1:0]

Output

Interrupt controller

Virtual FIQ to processors

nVIRQCPU[NUM_CPUS- 1:0]

Output

Interrupt controller

Virtual IRQ to processors

nFIQOUT[NUM_CPUS- 1:0]

Output

Interrupt controller

FIQ wakeup output

nIRQOUT[NUM_CPUS- 1:0]

Output

Interrupt controller

IRQ wakeup output

[a] NUM_CPUS and NUM_SPIS are set during configuration of the GIC-400.

[b] For information on the dedicated PPIs, see Interrupt inputs to the GIC-400.


Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0471B
Non-ConfidentialID081812
PDF file icon  PDF version
Home > Signal Descriptions > Interrupt signals