CoreLink™ GIC-400 Generic Interrupt Controller Technical Reference Manual

Revision: r0p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the GIC-400
1.2. Compliance
1.3. Interfaces
1.4. Configurable options
1.5. Product documentation
1.6. Product revisions
2. Functional Description
2.1. Functional overview of the GIC-400
2.1.1. Clock and reset
2.1.2. AXI4 interface
2.1.3. Distributor
2.1.4. CPU interfaces
2.1.5. Virtual CPU interfaces and virtual interface control registers
2.2. Secure and Non-secure access to the GIC-400
2.3. Interrupt inputs to the GIC-400
2.3.1. SGIs
2.3.2. PPIs
2.3.3. SPIs
2.3.4. Lockable SPIs (LSPIs)
2.4. Maintenance interrupts in the GIC-400
2.5. Virtual interrupts in the GIC-400
2.6. Interrupt handling and prioritization in the GIC-400
2.7. Power management
2.8. Behavior when the Distributor is disabled
3. Programmers Model
3.1. About the GIC-400 programmers model
3.2. GIC-400 register map
3.2.1. GIC-400 register access and banking
3.3. Distributor register summary
3.4. Distributor register descriptions
3.4.1. Distributor Implementer Identification Register, GICD_IIDR
3.4.2. Interrupt Configuration Registers, GICD_ICFGRn
3.4.3. Private Peripheral Interrupt Status Register, GICD_PPISR
3.4.4. Shared Peripheral Interrupt Status Registers, GICD_SPISRn
3.5. CPU interface register summary
3.6. CPU interface register descriptions
3.6.1. CPU Interface Identification Register, GICC_IIDR
3.7. GIC virtual interface control register summary
3.8. GIC virtual interface control register descriptions
3.8.1. VGIC Type Register, GICH_VTR
3.9. GIC virtual CPU interface register summary
3.10. GIC virtual CPU interface register descriptions
3.10.1. VM CPU Interface Identification Register, GICV_IIDR
A. Signal Descriptions
A.1. Clock and reset signals
A.2. Configuration signal
A.3. Interrupt signals
A.4. AXI slave interface signals
B. Interrupt Signaling
B.1. Interrupt signaling in the GIC-400 with physical interrupts only
B.2. Interrupt signaling in the GIC-400 with virtual interrupts
C. Revisions

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This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A23 June 2011First release for r0p0
Revision B07 August 2012First release for r0p1
Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0471B
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