CoreLink MMU-400 System Memory Management Unit Technical Reference ManualRevision: r0p0
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A.2.1. AXI3 signals

The following sections describe the AXI3 signals:

Table 1.2 and Table 1.3 describes the PTW width, master ID width, and slave ID width.

Write address channel signals

Table A.3 shows the AXI3 write address channel signals.

Table A.3. Write address channel signals

AMBA equivalentSlave port of TLB blockDirectionMaster Port of TLB blockDirectionMaster Port of PTWDirection
AWIDawid_s[I_S:0]Inputawid_m[I_M:0]Outputawid_ptw[I_P:0]Output
AWADDRawaddr_s[39:0]Inputawaddr_m[39:0]Outputawaddr_ptw[39:0]Output
AWLENawlen_s[3:0]Inputawlen_m[3:0]Outputawlen_ptw[3:0]Output
AWSIZEawsize_s[2:0]Inputawsize_m[2:0]Outputawsize_ptw[2:0]Output
AWBURSTawburst_s[1:0]Inputawburst_m[1:0]Outputawburst_ptw[1:0]Output
AWLOCKawlock_s[1:0]Inputawlock_m[1:0]Outputawlock_ptw[1:0]Output
AWCACHEawcache_s[3:0]Inputawcache_m[3:0]Outputawcache_ptw[3:0]Output
AWPROTawprot_s[2:0]Inputawprot_m[2:0]Outputawprot_ptw[2:0]Output
AWVALIDawvalid_s[0]Inputawvalid_m[0]Outputawvalid_ptw[0]Output
AWUSERawuser_s[AWUSER_WIDTH-1:0][a]Inputawuser_m[AWUSER_WIDTH+5:0]Output--
AWREADYawready_s[0]Outputawready_m[0]Inputawready_ptw[0]Input

[a] AWUSER_WIDTH is the width of AXI slave interface AWUSER signal.


Note

The PTW signals are present only when separate AXI configuration option is selected.Also write address, write data, and write response signals of PTW are dummy signals that are connected internally to any logic.

Write data channel signals

Table A.4 shows the AXI3 write data channel signals for the slave port of TLB block.

Table A.4. Write data channel signals-slave port of TLB block

AMBA equivalentSlave port of TLB blockDirection
WIDwid_s[I_S:0]Input
WDATA
For 64-bit

The data width is wdata_s[63:0]

For 128-bit

The data width is wdata_s[127:0]

Input
WSTRB
For 64-bit

The data width is wstrb_s[7:0]

For 128-bit

The data width is wstrb_s[15:0]

Input
WLASTwlast_s[0]Input
WVALIDwvalid_s[0]Input
WUSERwuser_s[WUSER_WIDTH-1:0][a]Input
WREADYwready_s[0]Output

[a] WUSER_WIDTH is the width of AXI slave interface WUSER signal.


Table A.5 shows the AXI3 write data channel signals for the master port of TLB block.

Table A.5. Write data channel signals-master port of TLB block

AMBA equivalentMaster Port of TLB blockDirection
WIDwid_m[I_M:0]Output
WDATA
For 64-bit

The data width is wdata_m[63:0]

For 128-bit

The data width is wdata_m[127:0]

Output
WSTRB
For 64-bit

The data width is wstrb_m[7:0]

For 128-bit

The data width is wstrb_m[15:0]

Output
WLASTwlast_m[0]Output
WVALIDwvalid_m[0]Output
WUSERwuser_m[WUSER_WIDTH-1:0]Output
WREADYwready_m[0]Input

Table A.6 shows the AXI3 write data channel signals for the master port of PTW.

Table A.6. Write data channel signals-master port of PTW

AMBA equivalentMaster Port of PTWDirection
WID

wid_ptw[I_P:0]

Output
WDATA
For 64-bit

The data width is wdata_ptw[63:0]

For 128-bit

The data width is wdata_ptw[127:0]

Output
WSTRB
For 64-bit

The data width is wstrb_ptw[7:0]

For 128-bit

The data width is wstrb_ptw[15:0]

Output
WLASTwlast_ptw[0]Output
WVALIDwvalid_ptw[0]Output
WUSER--
WREADYwready_ptw[0]Input

Write response channel signals

Table A.7 shows the AXI3 write response channel signals.

Table A.7. Write response channel signals

AMBA equivalentSlave port of TLB blockDirectionMaster port of TLB blockDirectionMaster port of PTWDirection
BIDbid_s[I_S:0]Outputbid_m[I_M:0]Inputbid_ptw[I_P:0]Input
BRESPbresp_s[1:0]Outputbresp_m[1:0]Inputbresp_ptw[1:0]Input
BVALIDbvalid_s[0]Outputbvalid_m[0]Inputbvalid_ptw[0]Input
BUSERbuser_s[BUSER_WIDTH-1:0][a]Outputbuser_m[BUSER_WIDTH-1:0]Input--
BREADYbready_s[0]Inputbready_m[0]Outputbready_ptw[0]Output

[a] BUSER_WIDTH is the width of AXI slave interface BUSER signal.


Read address channel signals

Table A.8 shows the AXI3 read address channel signals.

Table A.8. Read address channel signals

AMBA equivalentSlave port of TLB blockDirectionMaster port of of TLB blockDirectionMaster port of PTWDirection
ARIDarid_s[I_S:0]Inputarid_m[I_M:0]Outputarid_ptw[I_P:0]Output
ARADDRaraddr_s[39:0]Inputaraddr_m[39:0]Outputaraddr_ptw[39:0]Output
ARLENarlen_s[3:0]Inputarlen_m[3:0]Outputarlen_ptw[3:0]Output
ARSIZEarsize_s[2:0]Inputarsize_m[2:0]Outputarsize_ptw[2:0]Output
ARBURSTarburst_s[1:0]Inputarburst_m[1:0]Outputarburst_ptw[1:0]Output
ARLOCKarlock_s[1:0]Inputarlock_m[1:0]Outputarlock_ptw[1:0]Output
ARCACHEarcache_s[3:0]Inputarcache_m[3:0]Outputarcache_ptw[3:0]Output
ARPROTarprot_s[2:0]Inputarprot_m[2:0]Outputarprot_ptw[2:0]Output
ARVALIDarvalid_s[0]Inputarvalid_m[0]Outputarvalid_ptw[0]Output
ARUSERaruser_s[ARUSER_WIDTH-1:0][a]Inputaruser_m[ARUSER_WIDTH+5:0]Outputaruser_ptw[5:0]Output
ARREADYarready_s[0]Outputarready_m[0]Inputarready_ptw[0]Input

[a] ARUSER_WIDTH is the width of AXI slave interface ARUSER signal.


Read data channel signals

Table A.9 shows the AXI3 read data channel signals for the slave port of TLB block.

Table A.9. Read data channel signals-slave port of TLB block

AMBA equivalentSlave port of TLB blockDirection
RIDrid_s[I_S:0]Output
RDATA
For 64-bit

The data width is rdata_s[63:0]

For 128-bit

The data width is rdata_s[127:0]

Output
RRESPrresp_s[1:0]Output
RLASTrlast_s[0]Output
RVALIDrvalid_s[0]Output
RUSERruser_s[RUSER_WIDTH-1:0][a]Output
RREADYrready_s[0]Input

[a] RUSER_WIDTH is the width of AXI slave interface RUSER signal.


Table A.10 shows the AXI3 read data channel signals for the master port of TLB block.

Table A.10. Read data channel signals-master port of TLB block

AMBA equivalentMaster port of TLB blockDirection
RIDrid_m[I_M:0]Input
RDATA
For 64-bit

The data width is rdata_m[63:0]

For 128-bit

The data width is rdata_m[127:0]

Input
RRESPrresp_m[1:0]Input
RLASTrlast_m[0]Input
RVALIDrvalid_m[0]Input
RUSERruser_m[RUSER_WIDTH-1:0]Input
RREADYrready_m[0]Output

Table A.11 shows the AXI3 read data channel signals for the master port of PTW.

Table A.11. Read data channel signals-master port of PTW

AMBA equivalentMaster port of PTWDirection
RIDrid_ptw[I_P:0]Input
RDATA
For 64-bit

The data width is rdata_ptw[63:0]

For 128-bit

The data width is rdata_ptw[127:0]

Input
RRESPrresp_ptw[1:0]Input
RLASTrlast_ptw[0]Input
RVALIDrvalid_ptw[0]Input
RUSER--
RREADYrready_ptw[0]Output

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