CoreLink MMU-400 System Memory Management Unit Technical Reference ManualRevision: r0p0
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3.9.2. Peripheral Identification registers

The Peripheral Identification registers, PID characteristics are:

Purpose

In PID, only bits [7:0] of each register are used, and the Peripheral ID registers 7-5 are RESERVED.

Attributes

See Peripheral and Component identification registers summary.

The following are the Peripheral Identification registers:

Peripheral Identification Register 0

Figure 3.26 shows the register bit assignments for PID Register 0.

Figure 3.26. PID Register 0 register bit assignments

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Table 3.38 shows the register bit assignments for PID Register 0.

Table 3.38. PID Register 0 register bit assignments

BitsNameReset valueDescription
[31:8]RESERVED-RESERVED.
[7:0]PartNumber00x80Middle and lower-packed BCD value of Device number [7:0].

Peripheral Identification Register 1

Figure 3.27 shows the register bit assignments for PID Register 1.

Figure 3.27. PID Register 1 register bit assignments

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Table 3.39 shows the register bit assignments for PID Register 1.

Table 3.39. PID Register 1 register bit assignments

BitsNameReset valueDescription
[31:8]RESERVED-RESERVED.
[7:4]JEP106 identity code0xBJEP106 identity code.
[3:0]PartNumber10x4Upper packed-BCD value of Device number [11:8].

Peripheral Identification Register 2

Figure 3.28 shows the register bit assignments for PID Register 2.

Figure 3.28. PID Register 2 register bit assignments

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Table 3.40 shows the register bit assignments for PID Register 2

Table 3.40. PID Register 2 register bit assignments

BitsNameReset valueDescription
[31:8]RESERVED-RESERVED.
[7:4]Revision0Revision number of Peripheral. It starts from 0x0.
[3]JEDEC1Always set, indicates that a JEDEC assigned value is used.
[2:0]JEP106 identity code011JEP106 identity code [6:4].

Peripheral Identification Register 3

Figure 3.29 shows the register bit assignments for PID Register 3.

Figure 3.29. PID Register 3 register bit assignments

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Table 3.41 shows the register bit assignments for PID Register 3

Table 3.41. PID Register 3 register bit assignments

BitsName Reset valueDescription
[31:8]RESERVED-RESERVED.
[7:4]RevAnd0RevAnds at top-level.
[3:0]Customer Modified0Customer modified number. It must be 0x0 from ARM.

Peripheral Identification Register 4

Figure 3.30 shows the register bit assignments for PID Register 4.

Figure 3.30. PID Register 4 register bit assignments

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Table 3.42 shows the register bit assignments for PID Register 4

Table 3.42. PID Register 4 register bit assignments

BitsNameReset valueDescription
[31:8]RESERVED-RESERVED.
[7:4]4KB Count.0x44KB Count.
[3:0]JEP106 continuation code.0x4JEP106 continuation code.

Peripheral Identification registers 5-7

Figure 3.31 shows the bit assignments for PID Registers 5-7.

Figure 3.31. PID register 5-7 bit assignments

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Table 3.43 shows the register bit assignments for PID Register 5-7

Table 3.43. PID register 5-7 bit assignments

BitsName Reset valueDescription
[31:0]RESERVED0RESERVED

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