CoreLink MMU-400 System Memory Management Unit Technical Reference ManualRevision: r0p0
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3.7.4. Performance Monitor Counter Enable Set and Clear registers

The Performance Monitor Counter Enable Set and Clear registers characteristics are:

Purpose

The Performance Monitor Counter Enable Set Register, PMCNTENSET is used to set the bits from the Counter Enable Register, CNTENR.

The Performance Monitor Counter Enable Clear Register, PMCNTENCLR is used to clear the bits, to read the value of the Counter Enable Register, CNTENR.

CNTENR is a 3-bit register. See Performance Monitor Control Register .

CNTENR is UNKNOWN on reset.

Attributes

Performance monitoring registers summary.

Figure 3.18 shows the Performance Monitor Counter Enable Set and Clear registers bit assignments.

Figure 3.18. Performance Monitor Counter Enable Set and Clear registers bit assignments

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Table 3.26 shows the Performance Monitor Counter Enable Set and Clear registers bit assignments.

Table 3.26. Performance Monitor Counter Enable Set and Clear registers bit assignments

BitsNameReset valueDescription
[31:3]RESERVED-UNK/SBZP.
[2:0]Event Counter EVCNTRq where q= overflow 0

Counter enable bit CNTENR[q], q refers to Event counter register EVCNTRq.

On reads, each counter enable bit returns the corresponding bit of CNTENR, whether read through PMCNTENSET, or PMCNTENCLR. The action on writes depends on the register written through.


Table 3.27 shows the read and write bit values for the PMCNTEN0 registers.

Table 3.27. Read and write bit values for the PMCNTENn registers

ValueMeaning on readsRegisterDescription
0Counter is disabled-No action, write is ignored.
1Counter is enabledPMCNTENSET0Enable counter. Set CNTENR bit to one.
  PMCNTENCLR0Disable counter. Set CNTENR bit to zero.

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