CoreLink MMU-400 System Memory Management Unit Technical Reference Manual: 3.3.4. Performance monitoring registers summary

Table 3.4 shows the performance monitoring registers in base offset order.

Table 3.4. Performance monitoring registers summary

Name	Type	S or NS	Offset	Description
PMEVCNTR0-2	RW	NS	`0x3000`-`0x3008`	Performance Monitor Event Count Register
PMEVTYPE0-2	RW	NS	`0x3400`-`0x3408`	Performance Monitor Event Type Select Register
PMCGCR`n`	RW	NS	`0x3800`	Performance Monitor Counter Group Configuration Register
PMCGSMR`n`	RW	NS	`0x3A00`	Performance Monitor Counter Group Stream Match Register
PMCNTENSET`n`	RW	NS	`0x3C00`	Performance Monitor Counter Enable Set and Clear registers
PMCNTENCLR`n`	RW	NS	`0x3C20`
PMINTENSET`n`	RW	NS	`0x3C40`	Performance Monitor Interrupt Enable Set and Clear registers
PMINTENCLR`n`	RW	NS	`0x3C60`
PMOVSCLR`n`	RW	NS	`0x3C80`	Performance Monitor Overflow Status Set and Clear registers
PMOVSSET`n`	RW	NS	`0x3CC0`
PMCFGR	RO	NS	`0x3E00`	Performance Monitor Configuration Register
PMCR	RW	NS	`0x3E04`	Performance Monitor Control Register
PMCEID0-1	RO	NS	`0x3E20`-`0x3E24`	Performance Monitor Common Event ID Register
PMAUTHSTATUS	RO	NS	`0x3FB8`	Performance Monitor Authentication Status Register
PMDEVTYPE	RO	NS	`0x3FCC`	Performance Monitor Device Type Register

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