CoreLink MMU-400 System Memory Management Unit Technical Reference ManualRevision: r0p0
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3.10.2. Translation Table Base Control Register

The Translation Table Base Control Register characteristics are:

Purpose

SMMU_CBn_TTBCR, the Translation Table Base Control Register, provides additional configuration for the translation process.

Attributes

See Translation context bank registers summary.

Figure 3.33 shows the Translation Table Control Register bit assignments.

Figure 3.33. Translation Table Control Register bit assignments

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Table 3.47 shows the Translation Table Control Register bit assignments.

Table 3.47. Translation Table Control Register bit assignments

BitsNameDescription
[31]EAE (1)

Extended Address Enable.

This field always reads as the value 1. Writes are ignored.

A value of 1 means use the translation system defined in the LPAE.

[30:14]RESERVEDRESERVED.
[13:12]SH0Sharebility attributes for the memory associated with the translation table walks using TTBR0.
[11:10]ORGN0Outer cacheability attributes for the memory associated with the translation table walks using SMMU_CBn_TTBR0.
[9:8]IRGN0Inner cacheability attributes for the memory associated with the translation table walks using SMMU_CBn_TTBR0.
[7]SL0Reserved.
[6]

When bit [6] is 0, then the starting Level for SMMU_CBn_TTBR0 addressed region is Level 2.

When bit [6] is 1, then the starting Level for SMMU_CBn_TTBR0 addressed region is Level 1.

[5]RESERVEDRESERVED.
[4]S(0)

This bit must be programmed to T0SZ[3], or the effect is Unpredictable.

This bit is a sign extension of the T0SZ field, and is allocated this way for future compatibility for translation table systems with a larger input address.

[3:0]T0SZThe Size offset of the SMMU_CBn_TTBR0 addressed region, encoded as a 4 bits signed number giving the size of the region as 232-T0SZ.

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