CoreLink MMU-400 System Memory Management Unit Technical Reference Manual: 3.10.1. System Control Register

3.10.1. System Control Register

The System Control Register characteristics are:

Purpose: The System Control Register, SMMU_CBn_SCTLR, provides top-level control of the translation system for the related context bank.
Attribute: See Translation context bank registers summary.

Figure 3.32 shows the System Control Register bit assignment.

Figure 3.32. System Control Register bit assignment

Table 3.44 shows the System Control Register bit assignment.

Table 3.44. System Control Register bit assignment

Bits	Name	Reset value	Description
[31:28]	RESERVED	-	RESERVED.
[27:26]	WACFG	-	Write Allocate Configuration. The encodings of this field are: `00` Use the default allocation attributes. `01` RESERVED. `10` Write-Allocate. `11` No Write-Allocate. Note This field applies to the processing of transactions where the context bank translation is disabled, that is, where SMMU_CB`n`_SCTLR.M has the value 0.
[25:24]	RACFG	-	Read Allocate Configuration. Controls the allocation hint for read transactions where the context bank is disabled. The encodings of this field are: `00` Use the default allocation attributes. `01` RESERVED. `10` Read-Allocate. `11` No Read-Allocate. Note This field applies to the processing of transactions where the context bank translation is disabled, that is, where SMMU_CB`n`_SCTLR.M has the value 0.
[23:22]	SHCFG	-	Shared Configuration. Controls the shareable attributes for transactions where the context bank is disabled. The encodings of this field are: `00` Use shareable attribute as presented with transaction. `01` Outer Shareable. `10` Inner Shareable. `11` Non-shareable. Note This field applies to the processing of transactions where the context bank translation is disabled, that is, where SMMU_CB`n`_SCTLR.M has the value 0.
[21]	FB	-	Force Broadcast. This field forces the broadcast of TLB maintenance, BPIALL and ICIALLU operations.
[20]	RESERVED	-	RESERVED.
[19:16]	MemAttr	-	Memory Attribute. The memory attributes are permitted to be overlaid if SMMU_CB`n`_SCTLR.M has the value 0. Table 3.45 and Table 3.46 show valid values for this field
[15:14]	BSU	-	Barrier Shareability Upgrade. This field upgrades the required shareability domain of barriers issued by client devices mapped to this Stream mapping register group by setting the minimum shareability domain that is applied to any barrier. The encodings of this field are: `00` No effect. `01` Inner Shareable. `10` Outer Shareable. `11` Full system.
[13]	RESERVED	-	RESERVED.
[12:9]	RESERVED	-	RESERVED.
[8]	HUPCF	-	Hit Under Previous Context Fault. The possible values of this Hit-under-fault bit are: `0` Stall or terminate subsequent transactions in the presence of an outstanding context fault. `1` Process subsequent transactions independent of an outstanding context fault.
[7]	CFCFG	-	Context Fault Configuration. The possible value of this bit is: `0` Terminate.
[6]	CFIE	0	Context Fault Interrupt Enable. The possible values of this bit are: `0` Do not raise an interrupt when a Context fault occurs. `1` Raise an interrupt when a Context fault occurs. This field resets to the value 0.
[5]	CFRE	0	Context Fault Report Enable. The possible values of this bit are: `0` Do not return an abort when a Context fault occurs. `1` Return an abort when a Context fault occurs.
[4]	E	-	Endianess. This field indicates the endianess format of translation table entries. The possible values of this bit are: `0` Little Endian format. `1` Big Endian format.
[3]	AFFD	-	Access Flag Fault Disable. This field determines whether access flag faults are reported if they are raised. The possible values of this bit are: `0` Access flag faults are reported. `1` Access flag faults are not reported.
[2]	AFE	1	Access Flag Enable. This bit is UNK/SBOP.
[1]	TRE	1	TEX Remap Enable. This bit is UNK/SBOP.
[0]	M	0	MMU Enable. This is a global enable bit for the involved Translation context bank. The possible values of this bit are: `0` MMU behavior for this Translation context bank is disabled. `1` MMU behavior for this Translation context bank is enabled.

Table 3.45 shows MemAttr bit values

Table 3.45. MemAttr bit values

Bits[3:2]	Meaning
`0b00`	Strongly-ordered or device memory
`0b01`	Outer non-cacheable normal memory
`0b10`	Outer write-through normal memory
`0b11`	Outer write-back normal memory

Table 3.46 shows secondary MemAttr bit values

Table 3.46. Secondary MemAttr bit values

Bits[1:0]	Meaning when bits[3:2] == `00`	Meaning when bits[3:2] != `00`
`0b00`	Strongly-ordered	RESERVED
`0b01`	Device	Inner non-cacheable normal memory
`0b10`	RESERVED	Inner write-through normal memory
`0b11`	RESERVED	Inner write-back normal memory

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3.10.1. System Control Register

Note

Note

Note