CoreLink MMU-400 System Memory Management Unit Technical Reference ManualRevision: r0p0
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3.3.7. Translation context bank registers summary

Table 3.7 shows the translation context bank address map in base offset order.

Table 3.7. Translation context bank address map summary

NameTypeSizeOffsetDescription
SMMU_CBn_SCTLR RW320x0

System Control Register

SMMU_CBn_TTBR0[64:0]RW640x20-0x24

Translation Table Base Register

SMMU_CBn_TTBCRRW320x30

Translation Table Base Control Register

SMMU_CBn_FSR[a]--0x58Fault Status Register. See Table 3.1
SMMU_CBn_FSRRESTORE[a] --0x5CFault Status Restore Register. See Table 3.1
SMMU_CBn_FAR[31:0][a]--0x60Fault Address Register. See Table 3.1
SMMU_CBn_FAR[63:32][a]--0x64
SMMU_CBn_FSYNR0[a]--0x68Fault Syndrome Registers. See Table 3.1
SMMU_CBn_PMXEVCNTRm--0xE00-0xE08Performance Monitor Event Counter registers. See Performance Monitoring registers
SMMU_CBn_PMXEVTYPERm--0xE80-0xE88Performance Monitor Event Type Registers. See Performance Monitoring registers
SMMU_CBn_PMCFGR--0xF00Performance Monitor Configuration Register. See Performance Monitoring registers
SMMU_CBn_PMCR--0xF04Performance Monitor Control Register. See Performance Monitoring registers
SMMU_CBn_PMCEID0-1--0xF20Performance Monitor Common Event Identification registers. See Performance Monitoring registers
SMMU_CBn_PMCNTENSET--0xF40Performance Monitor Count Enable Set Register. See Performance Monitoring registers
SMMU_CBn_PMCNTENCLR--0xF44Performance Monitor Count Enable Clear Register. See Performance Monitoring registers
SMMU_CBn_PMINTENSET --0xF48Performance Monitor Interrupt Enable Set Register. See Performance Monitoring registers
SMMU_CBn_PMINTENCLR--0xF4CPerformance Monitor Interrupt Enable Clear Register. See Performance Monitoring registers
SMMU_CBn_PMOVSRCLR--0xF54Performance Monitor Overflow Status Clear Register. See Performance Monitoring registers
SMMU_CBn_PMOVSRSET--0xF50Performance Monitor Overflow Status Set Register. See Performance Monitoring registers
SMMU_CBn_PMAUTHSTATUS--0xFB8Performance Monitor Authentication Status Register. See Performance Monitoring registers

[a] Follow the same format as The MMU-400 Global Register Space 0 describes.


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