CoreLink™ MMU-400 System Memory Management Unit Technical Reference Manual

Revision: r0p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the MMU-400
1.2. The MMU-400 translation process
1.3. Features of the MMU-400
1.4. Configurable options
1.4.1. MMU-400 configurability
1.4.2. Configuration method
1.5. Product revisions
2. Functional Description
2.1. About programming interfaces
2.1.1. APB interface
2.1.2. Address map
2.1.3. AXI3 support
2.1.4. AXI4 support
2.1.5. ACE-Lite support
2.2. Generation of stream ID
2.3. Generation of the SSD index
2.4. Determining the security state of masters
2.5. HUM
2.6. Fault handling
3. Programmers Model
3.1. About the programmers model
3.2. The MMU-400 address map
3.3. Register map
3.3.1. Global space 0 registers summary
3.3.2. Global space 1 registers summary
3.3.3. Integration register summary
3.3.4. Performance monitoring registers summary
3.3.5. The MMU-400 security state determination address space summary
3.3.6. Peripheral and Component identification registers summary
3.3.7. Translation context bank registers summary
3.4. The MMU-400 Global Register Space 0
3.4.1. Secure Configuration Register 0
3.4.2. Auxiliary Configuration Register
3.4.3. Identification registers
3.4.4. Debug registers
3.4.5. Secure Alias to Non-secure Configuration Register 0
3.4.6. Secure Alias to Non-secure Auxiliary Configuration Register
3.4.7. Stream Match registers
3.4.8. Stream to Context registers
3.5. The MMU-400 Global Register Space 1
3.5.1. Context Bank Fault Restricted Syndrome Register A
3.5.2. Context Bank Attribute Register
3.6. Integration registers
3.6.1. Integration Mode Control Register
3.6.2. Integration Test Input Register
3.6.3. Integration Test Output Register
3.7. Performance Monitoring registers
3.7.1. Performance Monitor Event Count Register
3.7.2. Performance Monitor Counter Group Configuration Register
3.7.3. Performance Monitor Counter Group Stream Match Register
3.7.4. Performance Monitor Counter Enable Set and Clear registers
3.7.5. Performance Monitor Interrupt Enable Set and Clear registers
3.7.6. Performance Monitor Overflow Status Set and Clear registers
3.7.7. Performance Monitor Configuration Register
3.7.8. Performance Monitor Control Register
3.7.9. Performance Monitor Authentication Status Register
3.7.10. Performance Monitor Device Type Register
3.8. The MMU-400 Security State Determination Address Space
3.9. Peripheral and Component Identification registers
3.9.1. Component Identification registers
3.9.2. Peripheral Identification registers
3.10. Translation Context-Bank registers
3.10.1. System Control Register
3.10.2. Translation Table Base Control Register
A. Signal Description
A.1. Clock and resets
A.2. AMBA signals
A.2.1. AXI3 signals
A.2.2. AXI4 signals
A.2.3. ACE-Lite signals
A.2.4. APB signals
A.2.5. LPI signals
A.2.6. Snoop channel signals
A.3. Non-AMBA signals
A.3.1. Sideband signals
A.3.2. Interrupt signals
A.3.3. MBIST signals
A.3.4. Authentication interface signal
A.3.5. Tie-off signals
A.3.6. Performance event signals
B. Revisions

List of Figures

1. Key to timing diagram conventions
3.1. The MMU-400 address map, global space and translation context bank
3.2. Secure Configuration Register 0 bit assignments
3.3. Auxiliary Configuration Register bit assignments
3.4. Identification Register 0 bit assignments
3.5. Identification Register 1 bit assignments
3.6. Identification Register 2 bit assignments
3.7. Identification Register 7 bit assignments
3.8. Debug Read Pointer Register bit assignments
3.9. Stream Match registers bit assignments
3.10. Context Bank Restricted Syndrome Register bit assignments
3.11. Stage 2 Context, TYPE==00 Register bit assignments
3.12. ITCTRL Register bit assignments
3.13. ITIP Register bit assignments
3.14. ITOP Register bit assignments
3.15. Performance Monitoring Event Count Register
3.16. Performance Monitor Counter Group Configuration Register bit assignments
3.17. Performance Monitor Counter Group Stream Match Register bit assignments
3.18. Performance Monitor Counter Enable Set and Clear registers bit assignments
3.19. Performance Monitor Interrupt Enable Set and Clear registers bit assignments
3.20. Performance Monitor Overflow Flag Set and Clear registers bit assignments
3.21. Performance Monitor Configuration Register bit assignments
3.22. Performance Monitor Control Register format
3.23. Performance Monitor Authentication Status Register format
3.24. Performance Monitor Device Type Register bit assignments
3.25. CID registers 0-3 bit assignments
3.26. PID Register 0 register bit assignments
3.27. PID Register 1 register bit assignments
3.28. PID Register 2 register bit assignments
3.29. PID Register 3 register bit assignments
3.30. PID Register 4 register bit assignments
3.31. PID register 5-7 bit assignments
3.32. System Control Register bit assignment
3.33. Translation Table Control Register bit assignments

List of Tables

1.1. Configuration options for the MMU-400
1.2. The MMU-400 top configurability for TLB block
1.3. The MMU-400 top configurability for PTW block
3.1. Global space 0 registers summary
3.2. Global space 1 register summary
3.3. Integration registers summary
3.4. Performance monitoring registers summary
3.5. The MMU-400 security state determination address space summary
3.6. Peripheral and Component identification summary
3.7. Translation context bank address map summary
3.8. Secure Configuration Register 0 bit assignments
3.9. Auxiliary Configuration Register bit assignments
3.10. Identification Register 0 bit assignments
3.11. Identification Register 1 bit assignments
3.12. Identification Register 2 bit assignments
3.13. Identification Register 7 bit assignments
3.14. Debug Read Pointer Register bit assignments
3.15. Debug Read Data Register data format
3.16. Stream Match registers bit assignments
3.17. Context Bank Restricted Syndrome Register bit assignments
3.18. Context Bank Attribute Register
3.19. Stage 2 Context, TYPE==00 Register bit assignments
3.20. ITCTRL Register bit assignments
3.21. ITIP Register bit assignments
3.22. ITOP Register bit assignments
3.23. Performance Monitoring Event Count Register
3.24. Performance Monitor Counter Group Configuration Register bit assignments
3.25. Performance Monitor Counter Group Stream Match Register bit assignments
3.26. Performance Monitor Counter Enable Set and Clear registers bit assignments
3.27. Read and write bit values for the PMCNTENn registers
3.28. Performance Monitor Interrupt Enable Set and Clear registers bit assignments
3.29. Read and write bit values for the PMINTEN0 registers
3.30. Performance Monitor Overflow Flag Set and Clear registers bit assignments
3.31. Performance Monitor Configuration Register bit assignments
3.32. Performance Monitor Control Register format
3.33. Action on writes to the count enable bit
3.34. Performance Monitor Authentication Status Register format
3.35. Performance Monitor Device Type Register bit assignments
3.36. Security state determination address space
3.37. CID Register 0-3 register bit assignments
3.38. PID Register 0 register bit assignments
3.39. PID Register 1 register bit assignments
3.40. PID Register 2 register bit assignments
3.41. PID Register 3 register bit assignments
3.42. PID Register 4 register bit assignments
3.43. PID register 5-7 bit assignments
3.44. System Control Register bit assignment
3.45. MemAttr bit values
3.46. Secondary MemAttr bit values
3.47. Translation Table Control Register bit assignments
A.1. PTW block� clock and reset signals
A.2. �TLB block clock and reset signals
A.3. Write address channel signals
A.4. Write data channel signals-slave port of TLB block
A.5. Write data channel signals-master port of TLB block
A.6. Write data channel signals-master port of PTW
A.7. Write response channel signals
A.8. Read address channel signals
A.9. Read data channel signals-slave port of TLB block
A.10. Read data channel signals-master port of TLB block
A.11. Read data channel signals-master port of PTW
A.12. Write address channel signals
A.13. Write data channel signals-slave port of TLB block
A.14. Write data channel signals-master port of TLB block
A.15. Write data channel signals-master port of PTW
A.16. Write response channel signals
A.17. Read address channel signals
A.18. Read data channel signals
A.19. Write address channel signals
A.20. Write data channel signals-slave port of TLB block
A.21. Write data channel signals-master port of TLB block
A.22. Write data channel signals-master port of PTW
A.23. Write response channel signals
A.24. Read address channel signals
A.25. Read data channel signals
A.26. APB4 signals
A.27. APB3 signals
A.28. LPI signals
A.29. Snoop channel signals
A.30. Sideband signals
A.31. Interrupt signals
A.32. MBIST signals
A.33. Authentication Interface signal
A.34. Tie-off signals
A.35. Performance event signals
B.1. Issue A

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A07 October 2011Initial release for r0p0
Copyright © 2011 ARM. All rights reserved.ARM DDI 0472A
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