A.5.1. Master and Mirrored master signals

Table A.9 shows the protocol signals generated by a master. For more information on each signal see the AMBA 3 AHB-Lite Protocol Specification.

Table A.9. Master signals

AHB-Lite signal NIC-400 adaptation[a]DestinationDescription
haddr_x[b][n:0]Slave and decoder

System address bus.

Where:

n is equal to address width -1.

Address width is in the range of 32-64 bits.

hburst_x[b][2:0]SlaveThe burst type indicates if the transfer is a single transfer or forms part of a burst. Fixed length bursts of 4, 8, and 16 beats are supported.
hmastlock_x[b]SlaveWhen HIGH, this signal indicates that the current transfer is part of a locked sequence.
hprot_x[b][3:0]SlaveThe protection control signals provide additional information about a bus access and are primarily intended for use by any module that wants to implement some level of protection.
hsize_x[b][2:0]SlaveIndicates the size of the transfer.
htrans_x[b][1:0]SlaveIndicates the transfer type of the current transfer.
hwdata_x[b][n:0]Slave

Write data bus.

The write data bus transfers data from the master to the slaves during write operations.

Where:

n is equal to data width -1.

Data widths can be 32, 64, 128 or 256 bits.

hrdata_x[b][n:0]Master

Read data bus.

During read operations, the read data bus transfers data from the selected slave to the multiplexor. The multiplexor then transfers the data to the master.

Where:

n is equal to data width -1.

Data widths can be 32, 64, 128 or 256 bits.

hwrite_x[b]SlaveIndicates the transfer direction.
hready_x[b]SlaveWhen HIGH, the hready signal indicates to the master and all slaves, that the previous transfer is complete.
hresp_x[b]Master

The transfer response, after passing through the multiplexer, provides the master with additional information on the status of a transfer.

  • When LOW, the hresp signal indicates that the transfer status is OKAY

  • When HIGH, the hresp signal indicates that the transfer status is ERROR.

hwuser_x[b][n:0]Slave

Write data user defined signal.

Where:

n is equal to user defined width -1.

A user defined width in the range of 0-256 bits.

If 0 is selected then the signal is not used.

hruser_x[b][n:0]Master

Read data user defined signal.

Where:

n is equal to user defined width -1.

A user defined width in the range of 0-256 bits.

If 0 is selected then the signal is not used.

hauser_x[b][n:0]Slave

Address user defined signal.

Where:

n is equal to user defined width -1.

A user defined width in the range of 0-256 bits.

If 0 is selected then the signal is not used.

[a] Where:

You can select uppercase or lowercase signal names from the GUI.

[b] Where x is:

<port_name>_s

for a bridge slave interface

<port_name>_m

for a bridge master interface

<port_name>

for a system slave interface or master interface.


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