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Home > Signal Descriptions > AXI3 and AXI4 signals > Write data channel signals |
Table A.4 shows the AXI write data channel signals. Unless the description indicates otherwise, these signals are used by AXI3 and AXI4 protocols. For more information on each signal see the AMBA AXI and ACE Protocol Specification.
Table A.4. Write data channel signals
AXI signal NIC-400 adaptation[a] | Source | Description |
---|---|---|
wid_x[b][n:0] | Master | Write address ID. Where
NoteThis signal is not present in AXI4. |
wdata_x[b][n:0] | Master | Write data. Where:
Data widths can be 32, 64, 128 or 256 bits. |
wstrb_x[b][n:0] | Master | Write strobes When HIGH, specify the byte lanes of the data bus that contain valid information. There is one write strobe for each eight bits of the write data bus, therefore wstrb[n] corresponds to wdata[(8n)+7: (8n)]. |
wlast_x[b] | Master | Write last. |
wuser_x[b][n:0] | Master | User defined signal. Where:
A user defined width is in the range of 0-256 bits. If 0 is selected then the signal is not used. |
wvalid_x[b] | Master | Write valid. |
wready_x[b] | Slave | Write ready. |
[a] You can select uppercase or lowercase signal names from the GUI. [b] Where x is:
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