CoreLink NIC-400 Network Interconnect Technical Reference ManualRevision: r0p0
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A.3.2. Write data channel signals

Table A.4 shows the AXI write data channel signals. Unless the description indicates otherwise, these signals are used by AXI3 and AXI4 protocols. For more information on each signal see the AMBA AXI and ACE Protocol Specification.

Table A.4. Write data channel signals

AXI signal NIC-400 adaptation[a]SourceDescription
wid_x[b][n:0]Master

Write address ID.

Where n is a variable:

  • For an ASIB, ID width {0-16} where 0 indicates that no value has been selected.

  • For an AMIB, either:

    • Global ID width {1-24}

      or

    • if ID reduction has been selected, then the values can be viewed from the AMIBs ID reduction report from the GUI.

Note

This signal is not present in AXI4.

wdata_x[b][n:0]Master

Write data.

Where:

n is equal to data width - 1.

Data widths can be 32, 64, 128 or 256 bits.

wstrb_x[b][n:0]Master

Write strobes

When HIGH, specify the byte lanes of the data bus that contain valid information. There is one write strobe for each eight bits of the write data bus, therefore wstrb[n] corresponds to wdata[(8n)+7: (8n)].

wlast_x[b]MasterWrite last.
wuser_x[b][n:0]Master

User defined signal.

Where:

n is equal to user defined width -1.

A user defined width is in the range of 0-256 bits.

If 0 is selected then the signal is not used.

wvalid_x[b]MasterWrite valid.
wready_x[b]SlaveWrite ready.

[a] You can select uppercase or lowercase signal names from the GUI.

[b] Where x is:

<port_name>_s

for a bridge slave interface

<port_name>_m

for a bridge master interface

<port_name>

for a system slave interface or master interface.


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