2.2.3. Low-power interfaces, clock-gating

The AXI low-power interface, C channel, used in the hierarchical clock-gating feature contains the signals that Table 2.3 shows.

Table 2.3. AXI low-power interface

SignalDirectionSource, destinationDescription
CACTIVEOutput, inputInterconnect, controllerInterconnect active
CSYSREQOutput, inputController, interconnectSystem low-power request
CSYSACKOutput, inputInterconnect, controllerLow-power request acknowledgement

A low-power interface is present for each clock domain when hierarchical clock-gating is enabled. Hierarchical clock-gating is a global parameter in the NIC-400 configuration. Any slave interface that is configured as an AHB cannot support hierarchical clock gating completely because the protocol does not support it.

The AHB protocol expects a slave to take the address when issued. No mechanism exists for a slave to avoid this, so if the clock for an AHB interface was off, the address phase of the transfer is lost. Therefore, any AHB slave interface is required to be in its own unique clock domain.

To turn the AHB interface clock off, the system designer must ensure that no transactions are inhibited at this interface.

A CACTIVE output is provided to show the interface status.

The AMBA AXI and ACE Protocol Specification contains additional information on the function of these signals.

Note

You can treat the AXI AMBA AXI and ACE Protocol Specification description of the concept of CACTIVE being HIGH when CSYSACK falls as a denial of the request, with the clock continuing to run. It is not necessary to support this functionality when implementing clock-gating. When CSYSACK falls, it is always safe to gate the clock.

AMIBs with APB connections into another clock domain do not support hierarchical clock gating on that boundary. This is because of the large overhead of creating clock control circuitry for effectively one side of an APB asynchronous bridge. Therefore the system designer is responsible for ensuring that the clock is already enabled on this interface. The designer can achieve this in one of two ways:

These possible actions enable the NIC to wakeup and maintain the clock until the transaction is complete.

Copyright © 2012 ARM. All rights reserved.ARM DDI 0475A
Non-ConfidentialID081712