2.3.5. FIFO and clocking function

If you configure the network as a clock frequency crossing bridge, then a FIFO function is also configured.

Note

You can configure the buffering for multiple outstanding transactions even if you are using a 1:1 clocking ratio.

You can instantiate a FIFO on any channel. You can configure the FIFO to implement both buffering and clock domain crossing functionality. You can define the FIFO to be:

Note

You can dynamically change this through the GPV.

The network automatically determines that the width of the FIFO is the width of the widest payload, in or out of the block. You can configure the depth of the FIFO to be 2-32.

All clock boundary crossings are implemented using a FIFO structure with appropriate synchronization for the current mode of operation.

Changing the synchronization when you select programmable mode

You can change the boundary type by modifying the synchronization that is applied to the two pointers as they pass between domains. This ensures that the data in the FIFO is stable and safe to use.

To change the clocks, the synchronization must remain correct at all times. Table 2.10 shows the actions you must take to convert from one mode to another.

Table 2.10. How to change modes

Original modeRequired modeAction
ASYNCAny other modeChange the clocks then change the register.
Any modeASYNCChange the register then change ASYNC. BRESP from the GPV implies that the update is complete.
SYNC m:nSYNC 1:1Change the clocks, then change the register.
SYNC 1:1SYNC m:nChange the register, then change the clocks.

Note

For some changes, it is necessary to use a different setting, that is, you can only change safely from SYNC 1:n to SYNC m:1 by first programming the register to SYNC m:n, before the clock update.

Data release mechanism

When you configure a write data FIFO of at least 4, you can also set an additional write tidemark function, named wr_tidemark. This is a tidemark level that stalls the release of the transaction until:

  • The network receives the WLAST beat.

  • The write FIFO becomes full.

  • The number of occupied slots in the write data FIFO exceeds the write tidemark. See Chapter 3 Programmers Model.

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