2.3.11. Remap

Registers in the programmers model control the remap functionality. See Table 3.4 in Chapter 3 Programmers Model for more information.

You can define a number of remap states using eight bits of the remap register, and a bit in the remap register controls each remap state.

Note

You can use each remap state to control the address decoding for one or more slave interfaces. If a slave interface is affected by two remap states that are both asserted, the remap state with the lowest remap bit number takes precedence.

You can configure each slave interface independently so that a remap state can perform different functions for different masters.

A remap state can:

Because of the nature of the distributed register sub-system, the masters receive the updated remap bit states in sequence, and not simultaneously.

A slave interface does not update to the latest remap bit setting until:

Note

The BRESP from a GPV after a remap update guarantees that the next transaction issued to each slave interface, or the first one after the completion of a locked sequence, uses the updated value.

Figure 2.2 to Figure 2.6 show examples of how different remap states interact with each other. Consider a configuration that uses three remap bits. Figure 2.2 shows the memory map when remap is set to 000, representing no remap.

Figure 2.2. No remap, remap set to 000

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This has a default memory map that divides slave 0 and slave 3 into two separate regions. At power-up, slave 0 region 0 is aliased over slave 3 region 0. After power-up, the slave 0 region 0 alias can be removed as Figure 2.3 shows.

Figure 2.3. Remap set to 001

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Alternatively, you can move slave 1 to the bottom of the address range by setting remap to 010 as Figure 2.4 shows.

Figure 2.4. Remap set to 010

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Note

Remap bit 0 still takes precedence if you set it as Figure 2.5 shows.

Figure 2.5. Remap set to 011

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In addition, you can remove memory regions entirely. Figure 2.6 shows that if you set remap to 101, Slave 1 is removed.

Figure 2.6. Remap set to 101

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Copyright © 2012 ARM. All rights reserved.ARM DDI 0475A
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