A.3.1. Write address channel signals

Table A.3 shows the AXI write address channel signals. Unless the description indicates otherwise, these signals are used by AXI3 and AXI4 protocols. For more information on each signal, see the ARM® AMBA® AXI and ACE Protocol Specification.

Table A.3. Write address channel signals

AXI signal NIC-400 adaptation[a]SourceDescription

Write address ID.

Where n is a variable:

  • For an ASIB, ID width {0-16} where 0 indicates that no value has been selected.

  • For an AMIB, one of the following parameters:

    • Global ID width {1-24}.

    • ID reduction. If selected, then the values can be viewed in the AMIBs ID reduction report from the GUI.


Write address:


n is equal to address width -1.

Address width is in the range of 32-64 bits.

awlen_x[b][3:0]MasterBurst length for AXI3.
awlen_x[b][7:0]MasterBurst length for AXI4.
awsize_x[b][2:0]MasterBurst size.
awburst_x[b][1:0]MasterBurst type.
awlock_x[b][1:0]MasterLock type for AXI3.
awlock_xbMasterLock type for AXI4.
awcache_x[b][3:0]MasterMemory type.
awprot_x[b][2:0]MasterProtection type.
awqos_x[b][3:0]MasterQuality of Service, QoS. Only when enabled by the GUI.
awregion_x[b][3:0]MasterRegion identifier. Only when enabled by the GUI.

User definable signal.


n is equal to user defined width -1.

A user defined width is in the range of 0-256 bits.

awvalid_x[b]MasterWrite address valid.
awready_x[b]SlaveWrite address ready.

[a] You can select uppercase or lowercase signal names from the GUI.

[b] Where x is:


For a bridge slave interface.


For a bridge master interface.


For a system slave interface or master interface.

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