3.2.1. Register block types

The following types of register block exist:

Figure 3.1 shows the address map of the programmers model. It contains one fixed base address, and all the other programmers model 4KB blocks are stacked.

Figure 3.1. Address map of the programmers model

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The base address of a register block is determined by the node number assigned to it. There is no requirement for register blocks to be contiguous.

The number of register blocks present depends on the numbers of ASIBs, AMIBs, and IBs in the specific NIC-400 configuration. Table 3.1, Table 3.2, and Table 3.3 show the register block sub-types for each of the main types.

Table 3.4 shows the address region control registers and Table 3.5 shows the Peripheral ID registers.

Note

In Table 3.1 to Table 3.5, reserved means:

  • Read as zeros.

  • Writes are ignored.

AHB only means that this register is interpreted as reserved if the interface is not AHB.

Table 3.1 shows the registers that exist for each ASIB.

Table 3.1. Registers for each ASIB

Address

offset

TypeWidth

Reset

value

NameDescription
0x000----Reserved, 32-bit.
0x004----Reserved, 32-bit.
0x008----Reserved, 32-bit.
0x00C----Reserved, 32-bit.
0x020RW34sync_mode

This register is only present if a programmable clock crossing is configured across the ASIB. Select the required function by programming the register value as follows:

0

sync 1:1.

1

sync m:1.

2

sync 1:n.

3

sync m:n.

4

async.

5

reserved.

6

reserved.

7

reserved.

0x024RW10fn_mod2Bypass merge. This register is only present if upsizing or downsizing, see Upsizing data width function, Downsizing data width function, and Bypass merge.
0x028RW30fn_mod_ahb

This register is valid for AHB interfaces only. The register bits are active HIGH and have the following purpose:

0

rd_incr_override.

1

wr_incr_override.

2

lock_override.

See Lock transactions for information on overriding locks. See Combination 4 for information on wr_incr_override and rd_incr_override.

0x02CRW10fn_mod_lb

This register is only present when downsizing to AXI4 is required.

Long burst functionality modification register.

This controls burst breaking of long bursts as follows:

0

Long bursts cannot be generated at the output of the ASIB.

1

Long bursts can be generated at the output of the ASIB.

Note

If the programmers view is not turned on then the default value is used, and long bursts are not generated.

0x030 - 0x03C----Reserved.
0x040RW4[a]wr_tidemarkValid only with a FIFO for the WFIFO channel, where the tidemark value is configured to a non-zero value before RTL generation. See FIFO and clocking function for information on wr_tidemark.
0x044 - 0x0FC----Reserved.
0x100RW40[b]read_qos

Read channel QoS value.

This register is only present when the QoS settings for an ASIB (master) have been set to programmable.

0x104RW40[b]write_qos

Write channel QoS value.

This register is only present when the QoS settings for an ASIB (master) have been set to programmable.

0x108RW20fn_mod

Issuing functionality modification register. This register sets the block issuing capability to one outstanding transaction.The register bits are active high and have the following purpose:

0

Read issuing, read_iss_override.

1

Write issuing, write_iss_override.

0x10C ----Reserved.
0x114 - 0xFFC----Reserved.

[a] The reset value is initialized to the tidemark value that you set in the configuration GUI in CoreLink ADR-400 AMBA Designer.

[b] If you set the QoS Type parameter to Programmable, you can set the reset value of this register yourself.


Table 3.2 shows the registers that exist for each IB.

Table 3.2. Registers for each IB

Address

offset

TypeWidth

Reset

value

NameDescription
0x000----Reserved.
0x004----Reserved.
0x008RW20fn_mod_bm_iss

Bus matrix issuing functionality modification register.

This register sets the issuing capability of the preceding switch arbitration scheme to 1. The register bits are active HIGH and have the following purpose:

0

Read issuing, read_iss_override.

1

Write issuing, write_iss_override.

0x00C----Reserved.
0x020RW34sync_mode

This register is only present if a programmable clock crossing is configured across the IB. Select the required clock boundary synchronization scheme by programming the register value as follows:

0

sync 1:1.

1

sync m:1.

2

sync 1:n.

3

sync m:n.

4

async.

5

reserved.

6

reserved.

7

reserved.

0x024RW10fn_mod2Bypass merge. This register is only present if upsizing or downsizing. See Upsizing data width function, Downsizing data width function, and Bypass merge.
0x028 ----Reserved.
0x02CRW10fn_mod_lb

This register is only present when downsizing to AXI4 is required.

Long burst functionality modification register.

This controls burst breaking of long bursts as follows:

0

Long bursts cannot be generated at the output of the IB.

1

Long bursts can be generated at the output of the IB.

Note

If the programmers view is not turned on then the default value is used, and long bursts are not generated.

0x030 - 0x03C----Reserved.
0x040RW4[a]wr_tidemarkValid only with a FIFO for the WFIFO channel, where the tidemark value has been configured to a non-zero value prior to RTL generation.
0x044----Reserved.
0x100----Reserved.
0x104----Reserved.
0x108RW20fn_mod

Issuing functionality modification register.

Issuing override, sets block issuing capability to one transaction. You can configure the bits in the following manner:

0

Read issuing, read_iss_override.

1

Write issuing, write_iss_override.

0x10C ----Reserved.
0x114 - 0xFFC----Reserved.

[a] The reset value is initialized to the tidemark value that you set in the configuration GUI in CoreLink ADR-400 AMBA Designer.


Table 3.3 shows the registers that exist for each AMIB.

Table 3.3. Registers for each AMIB

Address

offset

TypeWidth

Reset

value

NameDescription
0x000----Reserved.
0x004----Reserved.
0x008RW20fn_mod_bm_iss

Bus matrix issuing functionality modification register. This register is only present if the block is connected directly to a switch.

This register sets the issuing capability of the preceding switch arbitration scheme to 1. The register bits are active HIGH and have the following purpose:

0

Read issuing, read_iss_override.

1

Write issuing, write_iss_override.

0x00C----Reserved.
0x020RW34sync_mode

This register is only present if a programmable clock crossing is configured across the AMIB. Select the required clock boundary synchronization scheme by programming the register value as follows:

0

sync 1:1.

1

sync m:1.

2

sync 1:n.

3

sync m:n.

4

async.

5

reserved.

6

reserved.

7

reserved.

0x024RW10fn_mod2Bypass merge. This register is only present if upsizing or downsizing. See Upsizing data width function and Downsizing data width function.
0x028----Reserved.
0x02CRW10fn_mod_lb

This register is only present when downsizing to AXI4 is required.

Long burst functionality modification register.

This controls burst breaking of long bursts as follows:

0

Long bursts cannot be generated at the output of the AMIB.

1

Long bursts can be generated at the output of the AMIB.

Note

If the programmers view is not turned on then the default value is used, and long bursts are not generated.

0x030 - 0x03C----Reserved.
0x040RW4[a]wr_tidemarkValid only with a FIFO for the WFIFO channel, where the tidemark value has been configured to a non-zero value prior to RTL generation.
0x044RW20ahb_cntl

This register is available for AHB only. The register bits are active HIGH and have the following purpose:

0

decerr_en.

1

force_incr.

See AHB-Lite master interfaces.

0x100 - 0x104----Reserved.
0x108RW20fn_mod

Issuing functionality modification register. This register is only available if you are upsizing or downsizing, or you have a FIFO for any of the channels. This register sets the block issuing capability to be forced to one transaction. The register bits are active high and have the following purpose:

0

Read issuing, read_iss_override.

1

Write issuing, write_iss_override.

0x10C - 0xFFC----Reserved.

[a] The reset value is initialized to the tidemark value that you set in the configuration GUI in CoreLink ADR-400 AMBA Designer.


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