2.2.3. Low-power interfaces, clock-gating

The AXI low-power interface, C channel, used in the hierarchical clock-gating feature, contains the signals that Table 2.3 shows.

Table 2.3. AXI low-power interface

SignalDirectionSource, destinationDescription
CACTIVEOutput, inputInterconnect, controllerInterconnect active
CSYSREQOutput, inputController, interconnectSystem low-power request
CSYSACKOutput, inputInterconnect, controllerLow-power request acknowledgement

A low-power interface is present for each clock domain when hierarchical clock-gating is enabled. Hierarchical clock-gating is a global parameter in the NIC-400 configuration. Any slave interface that is configured as an AHB-Lite cannot support hierarchical clock-gating completely because the protocol does not support it.

The AHB-Lite protocol expects a slave to take the address when issued. No mechanism exists for a slave to avoid this, so if the clock for an AHB-Lite interface is off, the address phase of the transfer is lost. Therefore, any AHB-Lite slave interface is required to be in its own unique clock domain.

To turn the AHB-Lite interface clock off, the system designer must ensure that no transactions are inhibited at this interface.

A CACTIVE output is provided to show the interface status. This is an additional signal provided specifically to support AHB-Lite. The interface status is whether the interface is busy or not, that is, whether CACTIVE is HIGH or LOW.

The ARM® AMBA® AXI and ACE Protocol Specification contains additional information on the function of these signals.


The ARM® AMBA® AXI and ACE Protocol Specification describes the case where CACTIVE can remain HIGH when CSYSACK falls, and you can interpret this as a denial of the request, with the clock continuing to run. It is not necessary to support this functionality when implementing clock-gating for the NIC-400. When CSYSACK falls, it is always safe to gate the clock.

AMIBs with APB connections into another clock domain do not support hierarchical clock-gating on that boundary. This is because of the large overhead of creating clock control circuitry for effectively one side of an APB asynchronous bridge. The system designer is therefore responsible for ensuring that the clock is already enabled on this interface. The system designer can achieve this in one of two ways:

Either of these solutions enables the NIC to wake up and maintain the clock until the transaction is complete.

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