2.2.2. Master interfaces

The CoreLink NIC-400 Network Interconnect supports the following master interfaces:

AXI3 and AXI4 master interfaces

The network supports the AXI protocol using an AXI master interface.

Note

Data widths of 512 or 1024 bits are not supported.

Configuration options

You can configure the following AXI options:

  • Address width of 32-64 bits.

  • Data width of 32, 64, 128, or 256 bits.

  • User sideband signal width of 0-256 bits.

  • Data width upsizer function that Upsizing data width function describes.

  • Data width downsizer function that Downsizing data width function describes.

  • Frequency domain crossing of type:

    • ASYNC.

    • SYNC 1:1.

    • SYNC 1:n.

    • SYNC n:1.

    • SYNC n:m.

  • Support for the full AXI protocol.

    Note

    • You can reduce the gate count and increase the performance if all attached masters that can access the master interface do not create any AXI lock transactions.

    • Data widths of 512 or 1024 bits are not supported.

  • Write issuing capability of 1-32 transactions.

    Note

    A switch before the AMIB does not issue more than two write address transfers without seeing the associated write data. This reduces the logic requirements in the switch and improves system QoS. It does not have an effect on throughput for the write channel.

  • Read issuing capability of 1-127 transactions.

    Note

    You can configure the read issuing capability as 0 when a master interface is not also configured as upsizing or downsizing, and when it is not converting between AXI3 and AXI4. The value of 0 removes any limiting of the read issuing capability by the interface. The read issuing capability is the sum of all upstream nodes that can access the interface.

  • Buffering that FIFO and clocking function describes.

  • Timing isolation:

    • From the external slave.

    • From the network.

  • AXI masters. You can reduce the number of ID bits exported at the master interface. See Global ID and ID reduction.

  • AXI region:

    • You can determine an AXI region value for a slave by applying an additional finer granularity at the address decode. Alternatively, you can input a region from the master. The AXI region is output to all slaves that have Multi-region Slave selected.

      Note

      You can select a 4-bit output region for a slave value, or you can input a region from the master interface.

    • If an APB slave is addressed, then an input region is overridden by the full address decode.

AHB-Lite master interfaces

The CoreLink NIC-400 Network Interconnect can support the full AHB-Lite protocol using either:

An AHB-Lite mirrored slave interface

This option provides all the AHB-Lite signals that a slave would have, which includes HSEL, HREADY input, and HREADY output signals. This enables the direct connection of an AHB-Lite slave to the NIC-400.

An AHB-Lite master interface

This option provides all the AHB-Lite signals that you would expect to see on an AHB-Lite master, so it does not have HSEL or HREADY output signals.

Note

The NIC-400 Network Interconnect requires a word invariant little endian data bus for AHB-lite interfaces.

Table 2.2 shows the mapping of AXI burst types to AHB-Lite burst types.

Table 2.2. AXI burst type to AHB-Lite burst type mapping

AxBURSTNumber of transfers in AXI transactionHBURSTNotes
FIXED-SINGLEThis is a series of singles, and the number depends on the AxLEN setting
INCR1SINGLE-
-4INCR4-
-8INCR8-
-16INCR16-
-

2, 3, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15

AXI4 extends burst length support for the INCR burst type to 2, 3, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 17-256

INCRUndefined length
WRAP2SINGLETwo transfers
WRAP4WRAP4-
-8WRAP8-
-16WRAP16-

Note

Transactions from AHB-Lite slave interfaces that are configured with early write response or broken bursts are output as INCR transactions of an undefined length.

If the AHB-Lite protocol conversion function receives an unaligned address, or a write data beat without all the byte strobes set, the CoreLink NIC-400 Network Interconnect detects it, and a programmable enable bit decerr_en permits the network to create a DECERR response. See Table 3.3.

The network still transmits the unaligned address transfer into the AHB-Lite domain, but it aligns the address by forcing the lower address bits of the size of the transaction to zeros.

Note

  • Because AHB-Lite does not support write data strobes when accessing AHB-Lite slaves from an AXI master, care must be taken not to generate transactions that have partial strobes. An example of this would be when a AXI master is accessing an AHB-Lite slave. Instead of issuing a single 32-bit transaction with WSTRB 00110 you must issue two 8-bit transactions.

  • If you set the force_incr programmable bit, and a beat is received that has no write data strobes set, that write data beat is replaced with an IDLE beat. For more information on the force_incr programmable bit see Table 3.3.

  • You can configure the inclusion of the programmable enable bit to create a reduced gate count implementation.

The network breaks any transactions that cross a 1KB boundary into multiple AHB-Lite INCR bursts. You can configure a programmable option, named force_incr. See Table 3.3. This option maps all transactions that are to be output to the AHB-Lite domain to be an undefined length INCR.

If the AXI burst is part of a locked sequence, the AHB-Lite translation keeps HMASTLOCK asserted across the boundary to ensure that the burst atomicity is not compromised. For write transactions, AHB-Lite responses are merged into a single AXI buffered response. The merged response is an AXI SLAVE ERROR if any of the AHB-Lite data beats have an AHB-Lite ERROR.

Any transaction that the network receives without all write data strobes asserted or negated still goes ahead. This means that erroneous data bytes might be written to the slave.

Configuration options

You can configure the following options for the AHB-Lite interface:

  • AHB-Lite master or mirrored slave interface types.

  • Address width of 32-64 bits.

  • Data width of 32, 64, 128, or 256 bits.

  • Data width upsizer function.

    Note

    AHB-Lite AMIB does not support data packing.

  • Data width downsizer function that Downsizing data width function describes.

  • Frequency domain crossing of the following types:

    • ASYNC.

    • SYNC 1:1.

    • SYNC 1:n.

    • SYNC n:1.

    • SYNC n:m.

  • Security of the following types:

    Secure

    Only Secure transactions can access components attached to this master interface.

    Non-secure

    Both Secure and Non-secure transactions can access components attached to this master interface.

    Boot Secure

    You can use software to configure whether Secure and Non-secure transactions are permitted to access components attached to this master using the Secure and Non-secure options.

  • Support for the full AHB-Lite master protocol.

  • Timing isolation:

    • From the external slave.

    • From the network.

    • User signals.

      Note

      HAUSER maps onto AWUSER or ARUSER internally depending on the access type.

      HWUSER maps onto WUSER.

      RUSER maps to HRUSER.

APB master interfaces

You can configure each APB interface to be of type APB2, APB3, or APB4. The APB data width is always 32 bits, and it is therefore never necessary for the APB interface to require the upsizer function. The APB interface can ignore AXI writes strobes. If the network receives a write transaction with all of the write strobes negated, then it does not perform the write.

Note

APB SLVERR responses are converted to AXI SLVERR responses.

Any transaction that the network receives without all four write data strobes asserted or negated still proceeds. This means that erroneous data bytes might be written to the APB3 or the ABP2 slaves.

Note

Because APB4 supports write strobes, the APB4 slave is unaffected by sparse data bytes.

The masters accessing the APB interface must ensure that only word writes access the APB sub-system. The address and data widths are fixed as follows:

  • Address width of 32 bits.

  • Data width of 32 bits.

Note

Although the CoreLink NIC-400 Network Interconnect only outputs 32 address bits, you can configure the APB address of any peripheral to be anywhere in the address map.

Configuration options

You can configure the following options:

  • Data width downsizer function as Downsizing data width function describes.

  • Frequency domain crossing for the majority of APB ports of the following types:

    • ASYNC.

    • SYNC 1:1.

    • SYNC 1:n.

    • SYNC n:1.

    • SYNC n:m.

  • Buffering as FIFO and clocking function describes.

  • 1-16 supported APB slaves.

  • Configurable address region sizes.

  • Non-contiguous address regions.

  • You can configure each APB slave for:

    • APB2, APB3, or APB4.

    • Asynchronous interface to the majority of APB ports.

  • Security of the following types:

    • Secure for each APB port.

    • Non-secure for each APB port.

    • Boot Secure for all APB ports.

    Note

    • To configure an APB port as Secure or Non-secure, the parent AMIB must have the TrustZone option configured as From Port. All other APB ports on that AMIB must also be configured to be Secure or Non-secure.

    • To configure an APB port as Boot Secure, all other APB ports in a group and the parent AMIB must be Boot Secure. The parent AMIB must also have the TrustZone option configured as Boot Secure.

    • For more information about TrustZone® technology and security, see TrustZone technology and security.

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