2.2.1. Slave interfaces

The CoreLink NIC-400 Network Interconnect supports the following slave interfaces:

Note

Any transaction that does not decode to a legal master interface destination, or to a register that is visible in the programmers model, receives a DECERR response. For an AHB-Lite master, the AXI DECERR is mapped to an AHB-Lite ERROR.

The AXI DECERR error is mapped to an AHB-Lite master ERROR if:

AXI3 and AXI4 slave interfaces

An AXI slave interface supports the AXI protocol.

Note

  • The NIC-400 base product does not accept, or issue, interleaved write data.

  • Data widths of 512 or 1024 bits are not supported.

Configuration options

You can configure the following options:

  • Address width of 32-64 bits.

  • Data width of 32, 64, 128, or 256 bits.

  • User sideband signal width of 0-256 bits.

  • Data width upsizer function. See Upsizing data width function.

  • Data width downsizer function. See Downsizing data width function.

  • Frequency domain crossing of the following types:

    • ASYNC.

    • SYNC 1:1.

    • SYNC 1:n.

    • SYNC n:1.

    • SYNC n:m.

  • Security of the following types:

    Secure

    All transactions originating from this slave interface are flagged as Secure transactions and can access both Secure and Non-secure components.

    Non-secure

    All transactions originating from this slave interface are flagged as Non-secure transactions and cannot access Secure components.

    Per access

    The AxPROT[1] signal determines the security setting of each transaction, and the slaves that it can access.

  • Support for the full AXI protocol.

    Note

    • Data widths of 512 or 1024 bits are not supported.

    • You can achieve a gate count reduction and a performance increase if the attached master does not create any AXI3 lock transactions.

  • Write acceptance capability of 1-32 transactions.

    Note

    If buffering components exist within the ASIB, then this value can be higher. For example, a full register slice in the slave interface position of the ASIB increases the write acceptance capability by two, and a forward register slice in the same position increases the write acceptance capability by one.

  • Read acceptance capability of 1-127 transactions.

    Note

    If buffering components exist within the ASIB, then this value can be higher. For example, a full register slice in the slave interface position of the ASIB increases the read acceptance capability by two, and a forward register slice in the same position increases the read acceptance capability by one.

  • Buffering, see FIFO and clocking function.

  • Timing isolation:

    • From the external master.

    • From the network.

AHB-Lite slave interfaces

The CoreLink NIC-400 Network Interconnect can support the full AHB-Lite protocol using either:

An AHB-Lite slave interface

This option provides all the AHB-Lite signals that a slave would have, which includes HSEL, HREADY input, and HREADY output signals.

An AHB-Lite mirrored master interface

This option has no HSEL or HREADY input signal; it is designed to be connected directly to an AHB-Lite master.

Note

The NIC-400 Network Interconnect requires a word invariant little endian data bus for AHB-Lite interfaces.

The following configuration options can improve AHB-Lite to AXI performance, but cannot always be used robustly:

  • Early Write Response and INCR promotion.

  • Allow Broken Bursts.

If you configure the interface as an AHB-Lite mirror master interface, you cannot configure Allow Broken Bursts because the AHB-Lite protocol does not permit AHB-Lite masters to break bursts.

Table 2.1 shows the four combinations for the configuration of Early Write Response and INCR promotion and Allow Broken Bursts, and contains links to descriptions for each option.

Table 2.1. Combination of configuration parameters

Early Write Response and INCR promotionAllow Broken BurstsDescription of combination
ConfiguredNot configuredCombination 1
Not configuredConfiguredCombination 2
ConfiguredConfiguredCombination 3
Not configuredNot configuredCombination 4

Combination 1

If you configure Early Write Response and INCR promotion and do not configure Allow Broken Bursts then the network converts all:

  • AHB-Lite read fixed length bursts to AXI fixed length bursts.

  • AHB-Lite write fixed length bursts with HPROT[3] asserted to AXI fixed length bursts:

    • All AHB-Lite write data beats receive an automatic OKAY response from the bridge irrespective of the B-channel AXI response. This means that if the network receives an error response, it does not feed it back to the master.

    • The bridge can support up to five outstanding write accesses.

  • AHB-Lite write fixed-length bursts with HPROT[3] negated to AXI fixed length bursts, and only the last AHB-Lite write data beat receives the AXI buffered response for the complete AHB-Lite transaction.

  • AHB-Lite read INCR bursts with HPROT[3] asserted to AXI INCR4 bursts.

  • AHB-Lite write INCR bursts with HPROT[3] asserted to AXI INCR4 bursts, and all AHB-Lite write data beats receive an automatic OKAY response from the bridge, irrespective of the B-channel AXI response. This means that if the network receives an error response, it does not feed it back to the master.

  • Read INCR bursts with HPROT[3] negated to a series of AXI singles.

  • Write INCR bursts with HPROT[3] negated to a series of AXI singles, and each AHB-Lite write beat is acknowledged with the AXI buffered write response.

Combination 2

If you configure Allow Broken Bursts and do not configure Early Write Response and INCR promotion, the network converts all:

  • Read fixed length bursts with HPROT[3] asserted to AXI fixed length bursts.

  • Read fixed length bursts with HPROT[3] negated to AXI singles.

  • Write fixed length bursts with HPROT[3] asserted to AXI fixed length bursts, but only the last AHB-Lite write data beat receives the AXI buffered response for the whole AHB-Lite transaction. However, if the AHB-Lite burst is broken, then the network does not feed the AXI response back to the master.

  • Write fixed length bursts with HPROT[3] negated to AXI singles, and each AHB-Lite write beat is acknowledged with the AXI buffered write response.

  • Read INCR bursts to a series of AXI singles.

  • Write INCR bursts to a series of AXI singles, and each AHB-Lite write beat is acknowledged with the AXI buffered write response.

Combination 3

If you configure Early Write Response and INCR promotion configure Allow Broken Bursts then the network converts all:

  • Read fixed length bursts with HPROT[3] asserted to AXI fixed length bursts.

  • Read fixed length bursts with HPROT[3] negated to AXI singles.

  • Write fixed length bursts with HPROT[3] asserted to AXI fixed length bursts:

    • The bridge sends an automatic OKAY response to all the AHB-Lite write data beats, disregarding the B-channel AXI response. Therefore, if the network generates an error response, it does not feed it back to the master.

    • The bridge can support up to five outstanding write accesses because the RAW hazard detection function supports up to four transactions. A fifth write is issued, but the AHB-Lite write response is not issued until a slot is freed in the RAW hazard monitor.

  • Write fixed length bursts with HPROT[3] negated to AXI singles, and each AHB-Lite write beat is acknowledged with the AXI buffered write response.

  • Read INCR bursts with HPROT[3] asserted speculatively to AXI INCR4 bursts.

  • Write INCR bursts with HPROT[3] asserted speculatively to AXI INCR4 bursts, and all AHB-Lite write data beats receive an automatic OKAY response from the bridge irrespective of the B-channel AXI response. Therefore, if the network generates an error response, it does not feed it back to the master.

  • Read INCR bursts with HPROT[3] negated to a series of AXI singles.

  • Write INCR bursts with HPROT[3] negated to a series of AXI singles, and each AHB-Lite write beat is acknowledged with the AXI buffered write response.

Combination 4

If you do not configure Early Write Response and INCR promotion and do not configure Allow Broken Bursts then the network converts all:

  • Read fixed length bursts to AXI fixed length bursts.

  • Write fixed length bursts to AXI fixed length bursts, and only the last AHB-Lite write data beat receives the AXI buffered response for the whole AHB-Lite transaction.

  • Read INCR bursts to a series of AXI singles.

  • Write INCR bursts to a series of AXI singles, and each AHB-Lite write beat is acknowledged with the AXI buffered write response.

Note

If you select either the Early Write Response and INCR promotion or Allow Broken Bursts configuration options, or both, then the following programmable function override bits also exist:

rd_incr_override

Converts all AHB-Lite read transactions to a series of single beat AXI transactions.

wr_incr_override

Converts all AHB-Lite write transactions to a series of single beat AXI transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write response.

You can configure these bits through a Global Programmers View (GPV) port.

See Chapter 3 Programmers Model for more information.

Error response

If the AHB-Lite master cancels a burst when it receives an ERROR response, the bridge stalls the master until the network receives all the read data beats from the AXI domain. This is only possible with read transfers because AXI writes receive a response at the end of the burst only.

Note

When communicating with transfer-sensitive slave devices such as FIFOs, the master might not be aware of how many read data beats have been read.

Lock transactions

The only supported lock transactions are SWAP (SWP) locks. That is, a single locking read followed by a single unlocking write, with an undefined number of IDLE transactions in between.

Note

  • If the network receives a non-SWP lock sequence, it is possible for a network path to be stalled, particularly if an odd number of lock transactions is issued. The stall is canceled on the next transaction received that unlocks the stalled path.

  • When the read part of the SWP operation causes the accessed slave to generate an error, the error is only presented to the AHB-Lite master when the write that terminates the SWP operation has been issued.

If you configure lock support and a GPV, then a lock override function is also configured. You can program this option, named lock_override, to force no AXI lock transactions to be created. See Chapter 3 Programmers Model.

Configuration options

You can configure the following AHB-Lite options:

  • AHB-Lite slave or mirrored master interface types.

  • Address width of 32-64 bits.

  • Data width of 32, 64, 128, or 256 bits.

  • Data width upsizer function that Upsizing data width function describes.

  • Data width downsizer function that Downsizing data width function describes.

  • Frequency domain crossing of the following types:

    • ASYNC.

    • SYNC 1:1.

    • SYNC 1:n.

    • SYNC n:1.

    • SYNC n:m.

  • Security of the following types:

    Secure

    All transactions originating from this slave interface are flagged as Secure transactions and can access both Secure and Non-secure components.

    Non-secure

    All transactions originating from this slave interface are flagged as Non-secure transactions and cannot access Secure components.

  • Early Write Response and INCR promotion.

  • Permit broken bursts using the Allow Broken Bursts parameter.

  • Support for the full AHB-Lite protocol with only SWP locks.

    Note

    You can reduce the gate count and increase the performance if the attached master does not create any AHB-Lite lock transactions.

  • Timing isolation:

    • From the external master.

    • From the network.

    • User signals.

      Note

      HAUSER maps onto AWUSER or ARUSER internally depending on the access type.

      HWUSER maps onto WUSER.

      RUSER maps to HRUSER.

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