2.3.2. Hierarchical clock-gating

Hierarchical clock-gating is a feature that enables a system to transition to another power state. This can be a low-power state where, in low activity scenarios, the power that the clock tree consumes can be saved. Hierarchical clock-gating enables an external clock controller to individually request clock domains in the interconnect to block new transactions from entering the interconnect when there are no outstanding transactions within the clock domain. The domain then acknowledges that this process is complete and the clock controller is able to remove the clock. Giving control over individual clock domains permits flexible system design and therefore flexible power state design.

The programmers model is distributed throughout the interconnect and therefore generally through multiple clock domains. See Chapter 3 Programmers Model. When the hierarchical clock-gating feature is enabled, and more than one clock domain contains a view to a register that is visible in the programmers model or an access point, an additional clock domain is added to the interconnect. This clock domain distributes accesses to the programmers model between the user-specified clock domains. It automatically requests the clock for other domains and makes clock-gating transparent to you when accessing the programmers model. This additional clock domain also has an AXI low-power interface that must be connected to a clock controller in the same way as the other interfaces. All communication between clock domains is carried out asynchronously so the clock frequency of this central ring can be set to what you require, within the limits of bridge limitations stated in the documentation.

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