ARM® CoreLink™ NIC-400 Network Interconnect Technical Reference Manual

Revision: r0p3

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About the CoreLink NIC-400 Network Interconnect
1.2. Key features
1.3. Relationship between NIC-400 and AMBA Designer
1.3.1. CoreLink NIC-400 Network Interconnect documentation
1.3.2. AMBA Designer documentation
1.3.3. Documentation for optional CoreLink features
1.4. Product revisions
2. Functional Description
2.1. About the functions
2.2. Interfaces
2.2.1. Slave interfaces
2.2.2. Master interfaces
2.2.3. Low-power interfaces, clock-gating
2.3. Operation
2.3.1. AXI3 and AXI4 protocol conversion
2.3.2. Hierarchical clock-gating
2.3.3. Upsizing data width function
2.3.4. Downsizing data width function
2.3.5. FIFO and clocking function
2.3.6. Arbitration
2.3.7. Cyclic Dependency Avoidance Schemes (CDAS)
2.3.8. Single Active Slave
2.3.9. Lock support
2.3.10. TrustZone technology and security
2.3.11. Remap
2.3.12. Global ID and ID reduction
2.4. Optional features
2.4.1. QoS
2.4.2. QVN
2.4.3. TLX
3. Programmers Model
3.1. About the programmers model
3.2. Configuration programmers model
3.2.1. Register block types
3.2.2. Register blocks
A. Signal Descriptions
A.1. Global signals
A.1.1. Low-power interface signals
A.2. Signal direction
A.3. AXI3 and AXI4 signals
A.3.1. Write address channel signals
A.3.2. Write data channel signals
A.3.3. Write response channel signals
A.3.4. Read address channel signals
A.3.5. Read data channel signals
A.4. APB signals
A.5. AHB-Lite signals
A.5.1. Master and Mirrored master signals
A.5.2. Slave and Mirrored slave signals
A.6. QVN signals
A.6.1. AXI VN signals
B. Revisions

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A07 August 2012First release for r0p0
Revision B13 May 2013First release for r0p1
Revision C09 December 2013First release for r0p2
Revision D07 March 2014First release for r0p3
Revision E30 September 2014Second release for r0p3
Copyright © 2012-2014 ARM. All rights reserved.ARM DDI 0475E