Cortex-M™ System Design Kit Technical Reference Manual

Revision: r0p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Typographical Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the Cortex-M System Design Kit
1.2. Product revisions
2. Functional Description
2.1. About the Cortex-M System Design Kit components
2.2. Design components
2.2.1. Basic AHB components
2.2.2. APB components
2.2.3. Advanced AHB components
2.2.4. Behavioral memory models
2.3. Verification components
2.3.1. AHB protocol checker
2.3.2. AHB-Lite protocol checker
2.3.3. APB protocol checkers
2.3.4. AHB File Reader Bus Master (FRBM)
2.4. ID registers in programmable components
2.4.1. Modification of components
2.5. Use of OVL
3. Basic AHB Components
3.1. Example AHB slave
3.1.1. Programmers model
3.2. AHB default slave
3.3. AHB slave multiplexer
3.4. AHB master multiplexer
3.4.1. Arbitration scheme
3.4.2. HMASTERM output
3.5. AHB GPIO
3.5.1. Features of the GPIO
3.5.2. Programmers model
3.6. AHB to APB sync-down bridge
3.7. AHB to SRAM interface module
3.8. AHB to flash interface module
3.9. AHB timeout monitor
3.10. AHB to external SRAM interface
3.10.1. Signal descriptions
3.11. AHB bit-band wrapper for Cortex-M0 processor
3.11.1. Bit-banding
4. APB Components
4.1. Example APB slaves
4.1.1. Programmers model
4.2. Timer
4.2.1. Programmers model
4.2.2. Signal descriptions
4.3. UART
4.3.1. Programmers model
4.4. Dual-input timers
4.4.1. Functional description
4.4.2. Operation
4.4.3. Clocking
4.4.4. Programmers model
4.4.5. Signal descriptions
4.5. Watchdog
4.5.1. Programmers model
4.5.2. Signal descriptions
4.6. Slave multiplexer
4.7. Subsystem
4.7.1. Programmers model
4.7.2. Signal descriptions
4.7.3. APB test slave
4.8. Timeout monitor
5. Advanced AHB Components
5.1. Bus matrix
5.1.1. Key features
5.1.2. Bus matrix configurability
5.1.3. Bus matrix module
5.1.4. Operation
5.1.5. Programmers model
5.1.6. Block functionality
5.1.7. Arbitration and locked transfers
5.1.8. Address map
5.1.9. Signal descriptions
5.2. AHB upsizer
5.2.1. Overview
5.2.2. Method of using AHB upsizer
5.3. AHB downsizer
5.3.1. Overview
5.3.2. Programmers model
5.3.3. Signal descriptions
5.3.4. Using AHB downsizer
5.4. AHB to APB asynchronous bridge
5.4.1. Overview
5.4.2. Cross-clock domain handling in AHB to APB asynchronous bridge
5.5. AHB to AHB synchronous bridge
5.5.1. Overview
5.5.2. Using AHB to AHB synchronous bridge
5.6. AHB to AHB sync-down bridge
5.6.1. Overview
5.6.2. Using the AHB to AHB sync-down bridge
5.6.3. Optional write buffer
5.6.4. Synthesizing the AHB to AHB sync-down bridge
5.7. AHB to AHB sync-up bridge
5.7.1. Overview
5.7.2. Using the AHB to AHB sync-up bridge
5.7.3. Synthesizing the AHB to AHB sync-up bridge
6. Behavioral Memory Models
6.1. ROM model wrapper
6.2. RAM model wrapper
6.3. Behavioral SRAM model with AHB interface
6.4. 32-bit flash ROM behavioral model
6.4.1. Signal descriptions
6.5. SRAM synthesizable model
6.6. FPGA ROM
6.6.1. Signal descriptions
6.7. External asynchronous 8 bits SRAM
6.7.1. Signal descriptions
6.8. External asynchronous 16-bit SRAM
6.8.1. Signal descriptions
7. Verification Components
7.1. AHB protocol checker
7.2. AHB-Lite protocol checker
7.3. APB protocol checker
7.4. AHB FRBM
7.4.1. Programmers model
7.4.2. Command syntax
7.4.3. File preprocessing
A. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Cortex-M System Design Kit usage in various stages of a design process
1.2. Difference between the two versions of the design kit
3.1. Example AHB Slave
3.2. AHB default slave component
3.3. AHB slave multiplexer
3.4. Cascade connection
3.5. AHB master multiplexer
3.6. AHB GPIO control circuit and external interface
3.7. Masked access 1
3.8. Masked access 2
3.9. AHB to APB sync-down bridge
3.10. AHB to SRAM interface module
3.11. SRAM interface timing
3.12. AHB to flash interface module
3.13. AHB to flash read access timing
3.14. AHB timeout monitor
3.15. Use of AHB timeout monitor
3.16. AHB to external SRAM interface
3.17. External SRAM interface timing 1
3.18. External SRAM interface timing 2
3.19. AHB bit-band wrapper for Cortex-M0 processor
3.20. Bit-band mapping
4.1. Example APB3 slave
4.2. Example APB4 slave
4.3. APB timer
4.4. APB UART
4.5. APB UART buffering
4.6. Dual-input timer components
4.7. Free-running timer block
4.8. Prescale clock enable generation
4.9. TIMERXCONTROL Register bit assignments
4.10. TIMERXRIS Register bit assignments
4.11. TIMERXMIS Register bit assignments
4.12. TIMERITCR Register bit assignments
4.13. TIMERITOP Register bit assignments
4.14. Watchdog components
4.15. Watchdog operation flow diagram
4.16. WDOGCONTROL Register bit assignments
4.17. WDOGRIS Register bit assignments
4.18. WDOGMIS Register bit assignments
4.19. WDOGLOCK Register bit assignments
4.20. WDOGITCR Register bit assignments
4.21. WDOGITOP Register bit assignments
4.22. APB slave multiplexer
4.23. APB subsystem
4.24. APB timeout monitor
4.25. Use of APB timeout monitor
5.1. Bus matrix module components
5.2. Example bus matrix design configuration
5.3. Region equations
5.4. Address map at different remap states
5.5. AHB upsizer
5.6. Using AHB upsizer, type one
5.7. Using AHB upsizer, type two
5.8. Downsizer module
5.9. Using AHB downsizer, direct connection
5.10. Using AHB downsizer, multiple connection
5.11. Using HRESP in AHB downsizer
5.12. AHB to APB asynchronous bridge
5.13. Structure of AHB to APB asynchronous bridge
5.14. AHB to AHB synchronous bridge
5.15. Using AHB to AHB synchronous bridge
5.16. AHB to AHB sync-down bridge
5.17. Clock divide operation
5.18. Using AHB to AHB sync-down bridge
5.19. Synthesizing the AHB to AHB sync-down bridge
5.20. AHB to AHB sync-up bridge
5.21. Clock divide operation
5.22. Using AHB to AHB sync-up bridge
5.23. Combinational paths from slow AHB to fast AHB
6.1. Design of ahb_rom.v for AHB_ROM_NONE
6.2. Design of ahb_rom.v for AHB_ROM_BEH_MODEL
6.3. Design of ahb_rom.v for AHB_ROM_FPGA_SRAM_MODEL
6.4. Design of ahb_rom.v for AHB_ROM_FLASH32_MODEL
6.5. Design of ahb_ram.v for AHB_RAM_NONE
6.6. Design of ahb_ram.v for AHB_RAM_BEH_MODEL
6.7. Design of ahb_ram.v for AHB_RAM_FPGA_SRAM_MODEL
6.8. Design of ahb_ram.v for AHB_RAM_EXT_SRAM16_MODEL
6.9. Design of ahb_ram.v for AHB_RAM_EXT_SRAM8_MODEL
6.10. Behavioral SRAM model with AHB interface
6.11. 32 bits flash ROM behavioral model
6.12. FPGA SRAM
6.13. FPGA ROM
6.14. External asynchronous 8 bits SRAM
6.15. External asynchronous 16 bits SRAM
7.1. AHB protocol checker
7.2. AHB-Lite protocol checker
7.3. APB protocol checker for APB3
7.4. APB protocol checker for APB4
7.5. 32 bits AHB FRBM
7.6. 64 bits AHB FRBM
7.7. Write command timing
7.8. Read command timing
7.9. Sequential command timing
7.10. Busy transfer timing
7.11. Busy cycle timing
7.12. Idle transfer timing
7.13. Idle cycle timing
7.14. Poll command timing
7.15. Stimulus file conversion

List of Tables

1.1. Cortex-M System Design Kit usage in various stages of a design process
3.1. Example AHB slave characteristics
3.2. Example AHB slave memory map
3.3. AHB default slave characteristics
3.4. AHB slave multiplexer characteristics
3.5. AHB master multiplexer characteristics
3.6. GPIO characteristics
3.7. Interrupt generation
3.8. GPIO memory map
3.9. AHB to APB sync-down bridge characteristics
3.10. AHB to SRAM interface module characteristics
3.11. AHB to flash interface module characteristics
3.12. AHB timeout monitor characteristics
3.13. AHB to external SRAM interface characteristics
3.14. AHB to external SRAM interface signals
3.15. AHB bit-band wrapper for Cortex-M0 processor characteristics
4.1. Example APB slave characteristics
4.2. Example APB slave memory map
4.3. APB timer characteristics
4.4. APB timer memory map
4.5. APB timer signals
4.6. APB UART characteristics
4.7. APB UART memory map
4.8. Timer memory map
4.9. TIMERXCONTROL Register bit assignments
4.10. TIMERXRIS Register bit assignments
4.11. TIMERXMIS Register bit assignments
4.12. TIMERITCR Register bit assignments
4.13. TIMERITOP Register bit assignments
4.14. Timer signals
4.15. Watchdog unit memory map
4.16. WDOGCONTROL Register bit assignments
4.17. WDOGRIS Register bit assignments
4.18. WDOGMIS Register bit assignments
4.19. WDOGLOCK Register bit assignments
4.20. WDOGITCR Register bit assignments
4.21. WDOGITOP Register bit assignments
4.22. Watchdog unit signals
4.23. APB slave multiplexer characteristics
4.24. APB subsystem characteristics
4.25. APB subsystem memory map
4.26. APB subsystem IRQ assignments
4.27. APB subsystem clock and reset signals
4.28. APB subsystem UART signals
4.29. APB subsystem timer signals
4.30. APB subsystem watchdog signals
4.31. APB subsystem interrupt signal
4.32. APB subsystem APB expansion port signals
4.33. APB test slave memory map
4.34. APB timeout monitor characteristics
5.1. Bus matrix signals
5.2. AHB upsizer characteristics
5.3. AHB downsizer characteristics
5.4. Narrow transfer handling
5.5. Address line modification and data routing
5.6. Signal mapping when downsizer module is activated
5.7. Downsizer interface signals
5.8. AHB to APB asynchronous bridge characteristics
5.9. AHB to AHB synchronous bridge characteristics
5.10. AHB to AHB sync-down bridge characteristics
5.11. AHB to AHB sync-up bridge characteristics
6.1. ROM model wrapper characteristics
6.2. Configuration of ahb_rom.v
6.3. RAM model wrapper characteristics
6.4. Configuration of ahb_ram.v
6.5. Behavioral SRAM model with an AHB interface characteristics
6.6. 32 bits flash ROM behavioral model characteristics
6.7. 32 bits flash ROM behavioral model signals
6.8. FPGA SRAM characteristics
6.9. FPGA ROM characteristics
6.10. FPGA ROM signals
6.11. External asynchronous 8 bits SRAM characteristics
6.12. External asynchronous 8 bits SRAM signals
6.13. External asynchronous 16 bits SRAM characteristics
6.14. External asynchronous 16-bit SRAM signals
7.1. AHB protocol checker characteristics
7.2. AHB Verilog parameters
7.3. Use of property type parameters
7.4. AHB-Lite protocol checker characteristics
7.5. AHB-Lite Verilog parameter descriptions
7.6. Use of property type parameters
7.7. APB protocol checker characteristics
7.8. APB Verilog parameter descriptions
7.9. Use of property type parameters
7.10. FRBM characteristics
7.11. Stimulus command syntax
7.12. Command fields
7.13. Characters supported by comment command
7.14. Compatibility between versions of FRBM and fm2conv.pl
7.15. Compatibility between versions of stimulus file and fm2conv.pl
7.16. Preprocessor command-line options
7.17. fm2conv.pl error messages
7.18. fm2conv.pl warnings
7.19. Numbering scheme for bit 7, severity
7.20. Numbering scheme for bits [6:4] and [3:2], error and warning type and subtype
7.21. Numbering scheme for bits [1:0], enumerator
A.1. Differences between issue B and issue A

Proprietary Notice

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A14 March 2011First release for r0p0
Revision B16 June 2011Second release for r0p0
Copyright © 2011 ARM. All rights reserved.ARM DDI 0479B
Non-ConfidentialID070811