Arm® Cortex®-M System Design Kit Technical Reference Manual

Revision: r1p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Typographical Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the Cortex-M System Design Kit
1.2. Product revisions
2. Functional description
2.1. About the Cortex-M System Design Kit components
2.2. Design components
2.2.1. Basic AHB-Lite components
2.2.2. APB components
2.2.3. Advanced AHB-Lite components
2.2.4. Behavioral memory models
2.2.5. Verification components
2.3. ID registers in programmable components
2.3.1. Modification of components
2.4. Use of OVL
3. Basic AHB-Lite components
3.1. AHB default slave
3.2. AHB example slave
3.2.1. Programmers model
3.3. AHB slave multiplexer
3.4. AHB master multiplexer
3.4.1. Arbitration scheme
3.4.2. Limitations
3.4.3. HMASTERM output
3.5. AHB GPIO
3.5.1. Features of the GPIO
3.5.2. Programmers model
3.5.3. Component dependency
3.6. AHB to APB sync-down bridge
3.7. AHB to SRAM interface module
3.8. AHB to flash interface modules
3.9. AHB timeout monitor
3.10. AHB to external SRAM interface
3.10.1. Signal descriptions
3.11. AHB bit-band wrapper
3.11.1. Bit-banding
3.11.2. Limitations
4. APB components
4.1. APB example slaves
4.1.1. Programmers model
4.2. APB timer
4.2.1. Programmers model
4.2.2. Signal descriptions
4.3. APB UART
4.3.1. Programmers model
4.4. APB dual-input timers
4.4.1. Functional description
4.4.2. Operation
4.4.3. Clocking
4.4.4. Programmers model
4.4.5. Signal descriptions
4.5. APB watchdog
4.5.1. Programmers model
4.5.2. Signal descriptions
4.6. APB slave multiplexer
4.7. APB subsystem
4.7.1. Programmers model
4.7.2. Signal descriptions
4.7.3. APB test slave
4.8. APB timeout monitor
5. Advanced AHB-Lite components
5.1. AHB bus matrix
5.1.1. Key features
5.1.2. Bus matrix configurability
5.1.3. Bus matrix module
5.1.4. Operation
5.1.5. Programmers model
5.1.6. Block functionality
5.1.7. Arbitration and locked transfers
5.1.8. Address map
5.1.9. Signal descriptions
5.2. AHB upsizer
5.2.1. Overview
5.2.2. Method of using AHB upsizer
5.3. AHB downsizer
5.3.1. About the AHB downsizer
5.3.2. Limitations
5.3.3. Programmers model
5.3.4. Signal descriptions
5.3.5. Using AHB downsizer
5.4. AHB to APB asynchronous bridge
5.4.1. About the AHB to APB asynchronous bridge
5.4.2. Cross-clock domain handling in AHB to APB asynchronous bridge
5.5. AHB to AHB and APB asynchronous bridge
5.5.1. About the AHB to AHB and APB asynchronous bridge
5.5.2. Handling of transfers initiated while master side is still in reset
5.5.3. Bursts
5.5.4. Reset requirements
5.5.5. External clock gating using the active signals
5.5.6. Clock domain crossing
5.6. AHB to AHB synchronous bridge
5.6.1. About the AHB to AHB synchronous bridge
5.6.2. Using AHB to AHB synchronous bridge
5.6.3. Component dependency
5.7. AHB to AHB sync-down bridge
5.7.1. About the AHB to AHB sync-down bridge
5.7.2. Using the AHB to AHB sync-down bridge
5.7.3. Optional write buffer
5.7.4. Synthesizing the AHB to AHB sync-down bridge
5.7.5. Component dependency
5.8. AHB to AHB sync-up bridge
5.8.1. Overview of the AHB to AHB sync-up bridge
5.8.2. Using the AHB to AHB sync-up bridge
5.8.3. Synthesizing the AHB to AHB sync-up bridge
5.8.4. Component dependency
6. Behavioral memory models
6.1. ROM model wrapper
6.2. RAM model wrapper
6.3. Behavioral SRAM model with AHB interface
6.4. 32-bit flash ROM behavioral model
6.4.1. Signal descriptions
6.5. 16-bit flash ROM behavioral model
6.5.1. Signal descriptions
6.6. FPGA SRAM synthesizable model
6.6.1. Signal descriptions
6.7. FPGA ROM
6.7.1. Signal descriptions
6.8. External asynchronous 8-bit SRAM
6.8.1. Signal descriptions
6.9. External asynchronous 16-bit SRAM
6.9.1. Signal descriptions
7. Verification components
7.1. AHB-Lite protocol checker
7.2. APB protocol checker
7.3. AHB FRBM
7.3.1. Programmers model
7.3.2. Command syntax
7.3.3. File preprocessing
A. IP-XACT descriptions
A.1. About IP-XACT for the Cortex-M System Design Kit components
A.2. Location of the IP-XACT description files
A.3. Generating the IP-XACT description
A.3.1. Bus matrix generator script
A.4. Using the IP-XACT description
B. Modification rights for supplied components
C. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Cortex-M System Design Kit usage in various stages of a design process
1.2. Difference between the two versions of the design kit
3.1. AHB default slave component
3.2. AHB example slave
3.3. AHB slave multiplexer
3.4. Cascade connection
3.5. AHB master multiplexer
3.6. AHB GPIO control circuit and external interface
3.7. Masked access 1
3.8. Masked access 2
3.9. AHB to APB sync-down bridge
3.10. AHB to SRAM interface module
3.11. SRAM interface timing
3.12. AHB to flash interface module for 32-bit flash ROM
3.13. AHB to flash interface module for 16-bit flash ROM
3.14. AHB to flash read access timing
3.15. AHB timeout monitor
3.16. Use of AHB timeout monitor
3.17. AHB to external SRAM interface
3.18. External SRAM interface timing 1
3.19. External SRAM interface timing 2
3.20. AHB bit-band wrapper for Cortex-M0 and Cortex-M0+ processor
3.21. Bit-band mapping
4.1. APB3 example slave
4.2. APB4 example slave
4.3. APB timer
4.4. APB UART
4.5. APB UART buffering
4.6. APB dual-input timers
4.7. Free-running timer block
4.8. Prescale clock enable generation
4.9. TIMERXCONTROL register bit assignments
4.10. TIMERXRIS register bit assignments
4.11. TIMERXMIS register bit assignments
4.12. TIMERITCR register bit assignments
4.13. TIMERITOP register bit assignments
4.14. APB watchdog
4.15. Watchdog operation flow diagram
4.16. WDOGCONTROL register bit assignments
4.17. WDOGRIS register bit assignments
4.18. WDOGMIS register bit assignments
4.19. WDOGLOCK register bit assignments
4.20. WDOGITCR Register bit assignments
4.21. WDOGITOP register bit assignments
4.22. APB slave multiplexer
4.23. APB subsystem
4.24. APB timeout monitor
4.25. Use of APB timeout monitor
5.1. Bus matrix module components
5.2. Example bus matrix design configuration
5.3. Region equations
5.4. Address map at different remap states
5.5. AHB upsizer
5.6. Using AHB upsizer, type one
5.7. Using AHB upsizer, type two
5.8. AHB downsizer
5.9. Using AHB downsizer, direct connection
5.10. Using AHB downsizer, multiple connection
5.11. AHB to APB asynchronous bridge
5.12. Structure of AHB to APB asynchronous bridge
5.13. AHB to AHB and APB asynchronous bridge
5.14. Example reset synchronizer
5.15. AHB to AHB synchronous bridge
5.16. Using AHB to AHB synchronous bridge
5.17. AHB to AHB sync-down bridge
5.18. Clock divide operation
5.19. Using AHB to AHB sync-down bridge
5.20. Synthesizing the AHB to AHB sync-down bridge
5.21. AHB to AHB sync-up bridge
5.22. Clock divide operation
5.23. Using AHB to AHB sync-up bridge
5.24. Combinational paths from slow AHB to fast AHB
6.1. Design of cmsdk_ahb_rom.v for AHB_ROM_NONE
6.2. Design of cmsdk_ahb_rom.v for AHB_ROM_BEH_MODEL
6.3. Design of cmsdk_ahb_rom.v for AHB_ROM_FPGA_SRAM_MODEL
6.4. Design of cmsdk_ahb_rom.v for AHB_ROM_FLASH32_MODEL
6.5. Design of cmsdk_ahb_rom.v for AHB_ROM_FLASH16_MODEL
6.6. Design of cmsdk_ahb_ram.v for AHB_RAM_NONE
6.7. Design of cmsdk_ahb_ram.v for AHB_RAM_BEH_MODEL
6.8. Design of cmsdk_ahb_ram.v for AHB_RAM_FPGA_SRAM_MODEL
6.9. Design of cmsdk_ahb_ram.v for AHB_RAM_EXT_SRAM16_MODEL
6.10. Design of cmsdk_ahb_ram.v for AHB_RAM_EXT_SRAM8_MODEL
6.11. Behavioral SRAM model with AHB interface
6.12. 32-bit flash ROM behavioral model
6.13. 16-bit flash ROM behavioral model
6.14. FPGA SRAM
6.15. FPGA ROM
6.16. External asynchronous 8-bit SRAM
6.17. External asynchronous 16-bit SRAM
7.1. AHB-Lite protocol checker
7.2. APB protocol checker
7.3. 32-bit AHB FRBM
7.4. 64-bit AHB FRBM
7.5. Write command timing
7.6. Read command timing
7.7. Sequential command timing
7.8. Busy transfer timing
7.9. Busy cycle timing
7.10. Idle transfer timing
7.11. Idle cycle timing
7.12. Poll command timing
7.13. Stimulus file conversion
A.1. IP-XACT busdefs directory structure

List of Tables

1.
1.1. Cortex-M System Design Kit usage in various stages of a design process
3.1. AHB default slave characteristics
3.2. AHB example slave characteristics
3.3. AHB example slave memory map
3.4. AHB slave multiplexer characteristics
3.5. AHB master multiplexer characteristics
3.6. AHB GPIO characteristics
3.7. Interrupt generation
3.8. GPIO memory map
3.9. AHB to APB sync-down bridge characteristics
3.10. AHB to SRAM interface module characteristics
3.11. AHB to flash interface module for 32-bit flash ROM characteristics
3.12. AHB to flash interface module for 16-bit ROM characteristics
3.13. AHB timeout monitor characteristics
3.14. AHB to external SRAM interface characteristics
3.15. AHB to external SRAM interface signals
3.16. AHB bit-band wrapper for Cortex-M0 processor characteristics
4.1. APB example slave characteristics
4.2. APB example slave memory map
4.3. APB timer characteristics
4.4. APB timer memory map
4.5. APB timer signals
4.6. APB UART characteristics
4.7. APB UART memory map
4.8. APB dual-input timer characteristics
4.9. Timer memory map
4.10. TIMERXCONTROL register bit assignments
4.11. TIMERXRIS register bit assignments
4.12. TIMERXMIS register bit assignments
4.13. TIMERITCR register bit assignments
4.14. TIMERITOP register bit assignments
4.15. Timer signals
4.16. APB watchdog characteristics
4.17. Watchdog memory map
4.18. WDOGCONTROL register bit assignments
4.19. WDOGRIS register bit assignments
4.20. WDOGMIS register bit assignments
4.21. WDOGLOCK register bit assignments
4.22. WDOGITCR Register bit assignments
4.23. WDOGITOP register bit assignments
4.24. Watchdog unit signals
4.25. APB slave multiplexer characteristics
4.26. APB subsystem characteristics
4.27. APB subsystem memory map
4.28. APB subsystem IRQ assignments
4.29. APB subsystem clock and reset signals
4.30. APB subsystem UART signals
4.31. APB subsystem timer signals
4.32. APB subsystem watchdog signals
4.33. APB subsystem interrupt signal
4.34. APB subsystem APB expansion port signals
4.35. APB test slave memory map
4.36. APB timeout monitor characteristics
5.1. Bus matrix signals
5.2. AHB upsizer characteristics
5.3. AHB downsizer characteristics
5.4. Narrow transfer handling
5.5. Address line modification and data routing
5.6. Signal mapping when downsizer module is activated
5.7. Downsizer module signals
5.8. AHB to APB asynchronous bridge characteristics
5.9. AHB to AHB and APB asynchronous bridge characteristics
5.10. AHB to AHB synchronous bridge characteristics
5.11. AHB to AHB sync-down bridge characteristics
5.12. AHB to AHB sync-up bridge characteristics
6.1. ROM model wrapper characteristics
6.2. Configuration of cmsdk_ahb_rom.v
6.3. RAM model wrapper characteristics
6.4. Configuration of cmsdk_ahb_ram.v
6.5. Behavioral SRAM model with an AHB interface characteristics
6.6. 32-bit flash ROM behavioral model characteristics
6.7. 32-bit flash ROM behavioral model signals
6.8. 16-bit flash ROM behavioral model characteristics
6.9. 16-bit flash ROM behavioral model signals
6.10. FPGA SRAM characteristics
6.11. FPGA SRAM signals
6.12. FPGA ROM characteristics
6.13. FPGA ROM signals
6.14. External asynchronous 8-bit SRAM characteristics
6.15. External asynchronous 8-bit SRAM signals
6.16. External asynchronous 16-bit SRAM characteristics
6.17. External asynchronous 16-bit SRAM signals
7.1. AHB-Lite protocol checker characteristics
7.2. AHB-Lite Verilog parameter descriptions
7.3. Use of property type parameters
7.4. APB protocol checker characteristics
7.5. APB Verilog parameter descriptions
7.6. Use of property type parameters
7.7. FRBM characteristics
7.8. Stimulus command syntax
7.9. Command fields
7.10. Characters supported by comment command
7.11. Compatibility between versions of FRBM and fm2conv.pl
7.12. Compatibility between versions of stimulus file and fm2conv.pl
7.13. Preprocessor command-line options
7.14. fm2conv.pl error messages
7.15. fm2conv.pl warnings
7.16. Numbering scheme for bit 7
7.17. Numbering scheme for bits[6:4] and bits[3:2]
7.18. Numbering scheme for bits[1:0]
A.1. Location of the IP-XACT description file
A.2. Location of the generated IP-XACT files
B.1. Modification rights for components
C.1. Differences between issue A and issue B
C.2. Differences between issue B and issue C
C.3. Differences between issue C and issue D

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Revision History
Revision A14 March 2011First release for r0p0
Revision B16 June 2011Second release for r0p0
Revision C19 April 2013First release for r1p0
Revision D31 October 2017First release for r1p1
Copyright © 2011, 2013, 2017 Arm Limited (or its affiliates). All rights reserved.ARM DDI 0479D
Non-ConfidentialID110617