CoreSight SoC Technical Reference Manual: A.5.1. Trace Port Interface Unit signals

A.5.1. Trace Port Interface Unit signals

Table A.27 shows the TPIU signals.

Table A.27. TPIU signals

Name	Type	Clock domain	Description
AFREADYS	Input	ATCLK	ATB data flush complete for the master port.
ATBYTESS[1:0]	Input	ATCLK	ATB number of valid bytes, LSB aligned, on the slave port.
ATCLK	Input	ATCLK	ATB clock.
ATCLKEN	Input	ATCLK	ATB clock enable.
ATDATAS[31:0]	Input	ATCLK	ATB trace data on the slave port.
ATIDS[6:0]	Input	ATCLK	ATB ID for current trace data on slave port.
ATRESETn	Input	ATCLK	ATB reset for the ATCLK domain.
ATVALIDS	Input	ATCLK	ATB valid signals present on slave port.
EXTCTLIN[7:0]	Input	ATCLK	External control input.
FLUSHIN	Input	ATCLK	Flush input from the CTI.
PADDRDBG[11:2]	Input	PCLKDBG	Debug APB address bus.
PADDRDBG31	Input	PCLKDBG	Enables components to distinguish between internal accesses from system software, and external accesses from a debugger.
PCLKDBG	Input	PCLKDBG	Debug APB clock.
PCLKENDBG	Input	PCLKDBG	Debug APB clock enable.
PENABLEDBG	Input	PCLKDBG	Debug APB enable signal, indicates second and subsequent cycles.
PRESETDBGn	Input	PCLKDBG	Debug APB asynchronous reset.
PSELDBG	Input	PCLKDBG	Debug APB component select.
PWDATADBG[31:0]	Input	PCLKDBG	Debug APB write data bus.
PWRITEDBG	Input	PCLKDBG	Debug APB write transfer.
SE	Input	N/A	Scan enable.
TPCTL	Input	ATCLK	Tie-off to report presence of TRACECTL, static value.
TPMAXDATASIZE[4:0]	Input	ATCLK	Tie-off to report maximum number of pins on TRACEDATA, static value.
TRACECLKIN	Input	TRACECLKIN	Trace clock.
TRESETn	Input	TRACECLKIN	Trace clock asynchronous reset.
TRIGIN	Input	ATCLK	Trigger input from the CTI.
AFVALIDS	Output	ATCLK	ATB data flush request for the master port.
ATREADYS	Output	ATCLK	ATB transfer ready on slave port.
EXTCTLOUT[7:0]	Output	ATCLK	External control output.
FLUSHINACK	Output	ATCLK	Flush input acknowledgement.
PRDATADBG[31:0]	Output	PCLKDBG	Debug APB read data bus.
PREADYDBG	Output	PCLKDBG	Debug APB ready signal.
TRACECLK	Output	TRACECLKIN	Half the frequency of the exported trace port clock, TRACECLKIN.
TRACECTL	Output	TRACECLKIN	Trace port control.
TRACEDATA[31:0]	Output	TRACECLKIN	Trace port data.
TRIGINACK	Output	ATCLK	Trigger input acknowledgement.

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