CoreSight SoC Technical Reference Manual: 6.2.7. Timestamp interpolator

6.2.7. Timestamp interpolator

The Timestamp Interpolator takes in 64-bit timestamp values that change at every system clock (SCLK) tick, it outputs a modified count related to a second clock source FCLK, which is usually faster than SCLK. Both SCLK and FCLK are internally generated clocks based on the input clock clk.

Clock and reset

This component has a single clock domain, clk.This component has a single reset input, resetn - Asynchronous active-low reset input.

Functional interface

This component has:

a Wide Timestamp input interface that carries the un-interpolated timestamp values from the timestamp generator.
a Wide Timestamp output interface that carries the interpolated timestamp values.

Functional description

The Timestamp interpolator is compliant with the ARM Generic Timer specification. ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition includes the specification for the ARM Generic Timer. The following are some of the key characteristics of the Timestamp interpolator:

The Timestamp interpolator takes in 64-bit timestamp values that increment at every SCLK-tick. FCLK is usually faster than SCLK:
1. SCLK This is the slow clock on which the timestamp generator operates. SCLK is the clk port on the timestamp generator.
2. FCLK This is the fast local clock on which the timestamp interpolator operates. FCLK is the clk port on the timestamp interpolator.
The Interpolator discards the upper N bits, appends N bits from its internal incrementing logic, and sends out tsvalueintpb[63:0]. N is the number of interpolated timestamp bits that the system designer configures.
If the incoming timestamp value is 0, the timestamp interpolator drives the output value to 0.
The interpolated value changes on every rising edge of FCLK. The interpolated bits increment to ensure that they reach the maximum value when the higher order bits change in the incoming timestamp.
The timestamp interpolator resets the interpolated bits for every change detected in the incoming timestamp.
To enhance the linear accuracy of interpolation, the Timestamp Interpolator interpolates additional bits, M, but only uses the upper N-bits of the result. M is defined as 4 and it cannot be changed.
The timestamp interpolator ensures that the output timestamp value does not decrease, provided that the input timestamp value does not decrease with respect to its previous timestamp value.
At slower SCLK frequencies, the Timestamp generator counts in higher increments to compensate and maintain a constant speed relative to real time. In this scenario, the interpolator interpolates up to P additional bits. At run-time, the number of extra bits interpolated Q, in the range 0 to P.
The Timestamp interpolator locates the least-significant bit in the Timestamp generator value that changes to calculate Q. When SCLK is at its maximum frequency, Q is 0.

Interpolator behavior under special conditions:

If the tsvalueb input is 0, the timestamp interpolator drives 0 on tsvalueintpb output and waits for the next increment on tsvalueb input.
The incrementer saturates at the maximum value, when:
1. the incrementer reaches the maximum value for the calculated value of Q.
2. but the next timestamp value is not available on tsvalueb.
When the input clock ratio exceeds the value that you configured, the interpolator still operates at the configured value of clock ratio.
When SCLK is faster than FCLK, the interpolator does not interpolate and the tsvalueb value sampled on the input is driven on the tsvalueintpb output. Some values on tsvalueb input might be lost on the tsvalueintpb output because of the difference in the frequencies.

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