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3.13.39. Lock Access Register

The LAR Register characteristics are:

Purpose

Controls write access from self-hosted, on-chip accesses. The LAR Register does not affect the accesses using the external debugger interface.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all configurations.

Attributes

See the register summary in Table 3.119.

Figure 3.152 shows the bit assignments.

Figure 3.152. LAR Register bit assignments

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Table 3.158 shows the bit assignments.

Table 3.158. LAR Register bit assignments

BitsNameFunction
[31:0]KEY

When you write 0xC5ACCE55, subsequent write operations to this device are enabled. Any other value disables subsequent write operations.


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