CoreSight SoC Technical Reference ManualRevision: r1p0
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3.4. APB interconnect register summary

Table 3.23 shows the APB interconnect registers in offset order from the base memory address.

Table 3.23. APB interconnect register summary

Offset

Name

Type

Reset

Description

0x000-0x0FCROM_ENTRY_n[a]RO-[b]ROM table entry
0xFD0PIDR4ROunknown[c]Peripheral ID4 Register
0xFD4PIDR5RO0x00000000Peripheral ID5-7 Registers
0xFD8PIDR6RO0x00000000
0xFDCPIDR7RO0x00000000
0xFE0PIDR0RO-[d]Peripheral ID0 Register
0xFE4PIDR1ROunknown[e]Peripheral ID1 Register
0xFE8PIDR2ROunknown[f]Peripheral ID2 Register
0xFECPIDR3RO0x00000000Peripheral ID3 Register
0xFF0CIDR0RO0x0000000DComponent ID0 Register
0xFF4CIDR1RO0x00000090Component ID1 Register
0xFF8CIDR2RO0x00000005Component ID2 Register
0xFFCCIDR3RO0x000000B1Component ID3 Register

[a] Where n is 0-63.

[b] The reset value depends on the value of the MASTER_INTFn_BASE_ADDR parameter, where n is 0-63. See the CoreSight SoC User Guide for more information.

[c] See Table 3.25 for more information on the reset value and its dependencies.

[d] The reset value depends on the system configuration, and identifies this as either a generic ROM table or a top-level ROM table.

[e] See Table 3.28 for more information on the reset value and its dependencies.

[f] See Table 3.29 for more information on the reset value and its dependencies.


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