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| Home > Programmers Model > TPIU register descriptions > Supported Trigger Modes Register | |||
The Supported_trigger_modes Register characteristics are:
This register indicates the implemented trigger counter multipliers and other supported features of the trigger system.
There are no usage constraints.
This register is available in all configurations.
See the register summary in Table 3.173.
Figure 3.169 shows the bit assignments.
Table 3.176 shows the bit assignments.
Table 3.176. Supported_trigger_modes Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:18] | Reserved | - |
| [17] | TrgRun | A trigger has occurred but the counter is not at zero. The possible values are:
|
| [16] | TRIGGERED | A trigger has occurred and the counter has reached zero. The possible values are:
|
| [15:9] | Reserved | - |
| [8] | TCOUNT8 | Indicates whether an 8-bit wide counter register implemented. The possible values are:
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| [7:5] | Reserved | - |
| [4] | MULT64K | Indicates whether multiply the Trigger Counter by 65536 is supported. The possible values are:
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| [3] | MULT256 | Indicates whether multiply the Trigger Counter by 256 is supported. The possible values are:
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| [2] | MULT16 | Indicates whether multiply the Trigger Counter by 16 is supported. The possible values are:
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| [1] | MULT4 | Indicates whether multiply the Trigger Counter by 4 is supported. The possible values are:
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| [0] | MULT2 | Indicates whether multiply the Trigger Counter by 2 is supported. The possible values are:
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