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All the registers are described in ARM® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2.
The JTAG-AP control status word is used to configure and control transfers through the JTAG interface.
See DAP register summary for more information
Figure 3.204 shows the bit assignments.
Table 3.217 shows the bit assignments. The register must not be modified while there are outstanding commands in the Write FIFO.
Table 3.217. JTAG-AP CSW Register bit assignments
| Bits | Type | Name | Function |
|---|---|---|---|
| [31] | RO | SERACTV | JTAG serializer active. The reset value
is |
| [30:28] | RO | WFIFOCNT | Outstanding write FIFO byte count. The
reset value is |
| [27] | - | - | Reserved, SBZ. |
| [26:24] | RO | RFIFOCNT | Outstanding read FIFO byte count. The
reset value is |
| [23:4] | - | - | Reserved, SBZ. |
| [3] | RO | PORTCONNECTED | PORT connected. AND of portconnected inputs
of currently selected ports. The reset value is b0. |
| [2] | RO | SRSTCONNECTED[a] | SRST connected. AND of srstconnected inputs of currently selected ports. If multiple ports are selected, it is the AND of all the srstconnected inputs from the selected ports. The reset value is |
| [1] | RW | TRST_OUT | TRST assert, not self clearing. The JTAG TAP controller reset. The reset value is |
| [0] | RW | SRST_OUT | SRST assert, not self clearing. Core reset. The reset value is |
[a] SRSTCONNECTED is a strap pin on the multiplexer inputs. It is set to 1 to indicate that the target JTAG device supports individual SRST controls. | |||
Enables ports if connected and the slave port is currently enabled. The Port Select Register must be written when the TCK engine is idle, SERACTV=0, and WFIFO, WFIFOCNT=0, is empty. Writing at other times can generate unpredictable results.
See DAP register summary for more information
Figure 3.205 shows the bit assignments.
Table 3.218 shows the bit assignments.
Table 3.218. JTAG-AP Port Select Register bit assignments
| Bits | Type | Name | Function |
|---|---|---|---|
| [31:8] | - | - | Reserved SBZ. |
| [7:0] | RW | PORTSEL | Port Select. The reset value is |
The Port Status Register is a sticky register that captures the state of a connected and selected port on every clock cycle. If a connected and selected port is disabled or powered down, even transiently, the corresponding bit in the Port Status Register is set. It remains set until cleared by writing a one to the corresponding bit.
See DAP register summary for more information.
Figure 3.206 shows the bit assignments.
Table 3.219 shows the bit assignments.
Table 3.219. JTAG-AP Port Status Register bit assignments
| Bits | Type | Name | Function |
|---|---|---|---|
| [31:8] | - | - | Reserved, SBZ. |
| [7:0] | RW | PSTA | Port Status. The reset value is |
The
Byte FIFO registers are a word interface to one, two, three, or
four parallel byte entries in the byte command FIFO, LSB first.
The DAP internal bus is a 32-bit interface with no SIZE field. So,
an address decoding is used to designate size, because the JTAG-AP
engine JTAG protocol is byte encoded. Writes to the BFIFOx larger
than the current write FIFO depth stall on dapready in
normal mode. Reads to the BFIFOx larger than the current read FIFO
depth stall on dapready in normal
mode. For reads less than the full 32-bits, the upper bits are zero.
For example, for a 24-bit read, daprdata[31:24] is 0x00.
See DAP register summary for more information.
Figure 3.207 shows the bit assignments.
Table 3.220 shows the bit assignments.
Table 3.220. JTAG-AP Identification Register bit assignments
| Bits | Type | Name | Value | Function |
|---|---|---|---|---|
| [31:28] | RO | Revision | 0x2 | Revision 2 |
| [27:24] | RO | JEDEC bank | 0x4 | Designed by ARM |
| [23:17] | RO | JEDEC code | 0x3B | Designed by ARM |
| [16] | RO | Mem AP | 0x0 | Is a Mem AP |
| [15:8] | - | Reserved | 0x00 | - |
| [7:0] | RO | Identity value | 0x10 | JTAG-AP |
| Copyright © 2011-2012 ARM. All rights reserved. | ARM DDI 0480B |
| Non-Confidential | ID042612 |
| PDF version | |
| Home > Programmers Model > DAP register descriptions > JTAG-AP register descriptions |