CoreSight™ SoC Technical Reference Manual

Revision: r2p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About CoreSight SoC
1.1.1. CoreSight SoC features
1.1.2. Structure of CoreSight SoC
1.2. CoreSight SoC block summary
1.3. Typical CoreSight debugging environment
1.4. Product revisions
2. Functional Overview
2.1. DAP components
2.1.1. Serial Wire or JTAG - Debug Port
2.1.2. DAP bus interconnect
2.1.3. DAP asynchronous bridge
2.1.4. DAP synchronous bridge
2.1.5. JTAG - Access Port
2.1.6. Advanced eXtensible Interface - Access Port
2.1.7. Advanced High-performance Bus - Access Port
2.1.8. Advanced Peripheral Bus Access Port
2.1.9. APB Interconnect with ROM table
2.1.10. APB asynchronous bridge
2.1.11. APB synchronous bridge
2.2. Advanced Trace Bus interconnect components
2.2.1. ATB replicator
2.2.2. ATB funnel
2.2.3. ATB upsizer
2.2.4. ATB downsizer
2.2.5. ATB asynchronous bridge
2.2.6. ATB synchronous bridge
2.3. Timestamp components
2.3.1. Timestamp generator
2.3.2. Timestamp encoder
2.3.3. Narrow timestamp replicator
2.3.4. Narrow timestamp asynchronous bridge
2.3.5. Narrow timestamp synchronous bridge
2.3.6. Timestamp decoder
2.3.7. Timestamp interpolator
2.4. Trigger components
2.4.1. Cross Trigger Interface
2.4.2. Cross Trigger Matrix
2.5. Trace sink components
2.5.1. Trace Port Interface Unit
2.5.2. Embedded Trace Buffer
2.6. Authentication and event bridges
2.6.1. Authentication asynchronous bridge
2.6.2. Authentication synchronous bridge
2.6.3. Event asynchronous bridge
2.7. Granular Power Requestor
3. Programmers Model
3.1. About the programmers model
3.2. Granular Power Requestor (GPR) register summary
3.3. GPR register descriptions
3.3.1. Debug Power Request Register
3.3.2. Debug Power Acknowledge Register
3.3.3. Integration Mode Control Register
3.3.4. Claim Tag Set Register
3.3.5. Claim Tag Clear Register
3.3.6. Lock Access Register
3.3.7. Lock Status Register
3.3.8. Authentication Status Register
3.3.9. Device Architecture Register
3.3.10. Device Configuration Register
3.3.11. Device Type Identifier Register
3.3.12. Peripheral ID4 Register
3.3.13. Peripheral ID5-7 registers
3.3.14. Peripheral ID0 Register
3.3.15. Peripheral ID1 Register
3.3.16. Peripheral ID2 Register
3.3.17. Peripheral ID3 Register
3.3.18. Component ID0 Register
3.3.19. Component ID1 Register
3.3.20. Component ID2 Register
3.3.21. Component ID3 Register
3.4. APB interconnect register summary
3.5. APB interconnect register descriptions
3.5.1. ROM Table Entry
3.5.2. Peripheral ID4 Register
3.5.3. Peripheral ID5-7 registers
3.5.4. Peripheral ID0 Register
3.5.5. Peripheral ID1 Register
3.5.6. Peripheral ID2 Register
3.5.7. Peripheral ID3 Register
3.5.8. Component ID0 Register
3.5.9. Component ID1 Register
3.5.10. Component ID2 Register
3.5.11. Component ID3 Register
3.6. ATB funnel register summary
3.7. ATB funnel register descriptions
3.7.1. Funnel Control Register
3.7.2. Priority Control Register
3.7.3. Integration Test ATB Data0 Register
3.7.4. Integration Test ATB Control 2 Register
3.7.5. Integration Test ATB Control 1 Register
3.7.6. Integration Test ATB Control 0 Register
3.7.7. Integration Mode Control Register
3.7.8. Claim Tag Set Register
3.7.9. Claim Tag Clear Register
3.7.10. Lock Access Register
3.7.11. Lock Status Register
3.7.12. Authentication Status Register
3.7.13. Device Configuration Register
3.7.14. Device Type Identifier Register
3.7.15. Peripheral ID4 Register
3.7.16. Peripheral ID5-7 registers
3.7.17. Peripheral ID0 Register
3.7.18. Peripheral ID1 Register
3.7.19. Peripheral ID2 Register
3.7.20. Peripheral ID3 Register
3.7.21. Component ID0 Register
3.7.22. Component ID1 Register
3.7.23. Component ID2 Register
3.7.24. Component ID3 Register
3.8. ATB replicator register summary
3.9. ATB replicator register descriptions
3.9.1. ID filtering for ATB master port 0
3.9.2. ID filtering for ATB master port 1
3.9.3. Integration Mode ATB Control 0 Register
3.9.4. Integration Mode ATB Control 1 Register
3.9.5. Integration Mode Control Register
3.9.6. Claim Tag Set Register
3.9.7. Claim Tag Clear Register
3.9.8. Lock Access Register
3.9.9. Lock Status
3.9.10. Authentication Status Register
3.9.11. Device Configuration Register
3.9.12. Device Type Identifier Register
3.9.13. Peripheral ID4 Register
3.9.14. Peripheral ID5-7 Registers
3.9.15. Peripheral ID0 Register
3.9.16. Peripheral ID1 Register
3.9.17. Peripheral ID2 Register
3.9.18. Peripheral ID3 Register
3.9.19. Component ID0 Register
3.9.20. Component ID1 Register
3.9.21. Component ID2 Register
3.9.22. Component ID3 Register
3.10. ETB register summary
3.11. ETB register descriptions
3.11.1. ETB RAM Depth Register
3.11.2. ETB Status Register
3.11.3. ETB RAM Read Data Register
3.11.4. ETB RAM Read Pointer Register
3.11.5. ETB RAM Write Pointer Register
3.11.6. ETB Trigger Counter Register
3.11.7. ETB Control Register
3.11.8. ETB RAM Write Data Register
3.11.9. ETB Formatter and Flush Status Register
3.11.10. ETB Formatter and Flush Control Register
3.11.11. Integration Test Miscellaneous Output Register 0
3.11.12. Integration Test Trigger In and Flush In Acknowledge Register
3.11.13. Integration Test Trigger In and Flush In Register
3.11.14. Integration Test ATB Data Register 0
3.11.15. Integration Test ATB Control Register 2
3.11.16. Integration Test ATB Control Register 1
3.11.17. Integration Test ATB Control Register 0
3.11.18. Integration Mode Control Register
3.11.19. Claim Tag Set Register
3.11.20. Claim Tag Clear Register
3.11.21. Lock Access Register
3.11.22. Lock Status Register
3.11.23. Authentication Status Register
3.11.24. Device Configuration Register
3.11.25. Device Type Identifier Register
3.11.26. Peripheral ID4 Register
3.11.27. Peripheral ID5-7 registers
3.11.28. Peripheral ID0 Register
3.11.29. Peripheral ID1 Register
3.11.30. Peripheral ID2 Register
3.11.31. Peripheral ID3 Register
3.11.32. Component ID0 Register
3.11.33. Component ID1 Register
3.11.34. Component ID2 Register
3.11.35. Component ID3 Register
3.12. CTI register summary
3.13. CTI register descriptions
3.13.1. CTI Control Register
3.13.2. CTI Interrupt Acknowledge Register
3.13.3. CTI Application Trigger Set Register
3.13.4. CTI Application Trigger Clear Register
3.13.5. CTI Application Pulse Register
3.13.6. CTI Trigger 0 to Channel Enable Register
3.13.7. CTI Trigger 1 to Channel Enable Register
3.13.8. CTI Trigger 2 to Channel Enable Register
3.13.9. CTI Trigger 3 to Channel Enable Register
3.13.10. CTI Trigger 4 to Channel Enable Register
3.13.11. CTI Trigger 5 to Channel Enable Register
3.13.12. CTI Trigger 6 to Channel Enable Register
3.13.13. CTI Trigger 7 to Channel Enable Register
3.13.14. CTI Channel to Trigger 0 Enable Register
3.13.15. CTI Channel to Trigger 1 Enable Register
3.13.16. CTI Channel to Trigger 2 Enable Register
3.13.17. CTI Channel to Trigger 3 Enable Register
3.13.18. CTI Channel to Trigger 4 Enable Register
3.13.19. CTI Channel to Trigger 5 Enable Register
3.13.20. CTI Channel to Trigger 6 Enable Register
3.13.21. CTI Channel to Trigger 7 Enable Register
3.13.22. CTI Trigger In Status Register
3.13.23. CTI Trigger Out Status Register
3.13.24. CTI Channel In Status Register
3.13.25. CTI Channel Out Status Register
3.13.26. Enable CTI Channel Gate Register
3.13.27. External Multiplexer Control Register
3.13.28. Integration Test Channel Input Acknowledge Register
3.13.29. Integration Test Trigger Input Acknowledge Register
3.13.30. Integration Test Channel Output Register
3.13.31. Integration Test Trigger Output Register
3.13.32. Integration Test Channel Output Acknowledge Register
3.13.33. Integration Test Trigger Output Acknowledge Register
3.13.34. Integration Test Channel Input Register
3.13.35. Integration Test Trigger Input Register
3.13.36. Integration Mode Control Register
3.13.37. Claim Tag Set Register
3.13.38. Claim Tag Clear Register
3.13.39. Lock Access Register
3.13.40. Lock Status Register
3.13.41. Authentication Status Register
3.13.42. Device Configuration Register
3.13.43. Device Type Identifier Register
3.13.44. Peripheral ID4 Register
3.13.45. Peripheral ID5-7 Registers
3.13.46. Peripheral ID0 Register
3.13.47. Peripheral ID1 Register
3.13.48. Peripheral ID2 Register
3.13.49. Peripheral ID3 Register
3.13.50. Component ID0 Register
3.13.51. Component ID1 Register
3.13.52. Component ID2 Register
3.13.53. Component ID3 Register
3.14. TPIU register summary
3.15. TPIU register descriptions
3.15.1. Supported Port Size Register
3.15.2. Current Port Size Register
3.15.3. Supported Trigger Modes Register
3.15.4. Trigger Counter Value Register
3.15.5. Trigger Multiplier Register
3.15.6. Supported Test Patterns/Modes Register
3.15.7. Current Test Pattern/Modes Register
3.15.8. TPIU Test Pattern Repeat Counter Register
3.15.9. Formatter and Flush Status Register
3.15.10. Formatter and Flush Control Register
3.15.11. Formatter Synchronization Counter Register
3.15.12. TPIU EXCTL Port Register - In
3.15.13. TPIU EXCTL Port Register - Out
3.15.14. Integration Test Trigger In and Flush In Acknowledge Register
3.15.15. Integration Test Trigger In and Flush In Register
3.15.16. Integration Test ATB Data Register 0
3.15.17. Integration Test ATB Control Register 2
3.15.18. Integration Test ATB Control Register 1
3.15.19. Integration Test ATB Control Register 0
3.15.20. Integration Mode Control Register
3.15.21. Claim Tag Set Register
3.15.22. Claim Tag Clear Register
3.15.23. Lock Access Register
3.15.24. Lock Status Register
3.15.25. Authentication Status Register
3.15.26. Device Configuration Register
3.15.27. Device Type Identifier Register
3.15.28. Peripheral ID4 Register
3.15.29. Peripheral ID5-7 registers
3.15.30. Peripheral ID0 Register
3.15.31. Peripheral ID1 Register
3.15.32. Peripheral ID2 Register
3.15.33. Peripheral ID3 Register
3.15.34. Component ID0 Register
3.15.35. Component ID1 Register
3.15.36. Component ID2 Register
3.15.37. Component ID3 Register
3.16. DAP register summary
3.16.1. JTAG-AP register summary
3.16.2. AHB-AP register summary
3.16.3. AXI-AP register summary
3.16.4. APB-AP register summary
3.16.5. Debug port register summary
3.17. DAP register descriptions
3.17.1. JTAG-AP register descriptions
3.17.2. AHB-AP register descriptions
3.17.3. AXI-AP register descriptions
3.17.4. APB-AP register descriptions
3.17.5. Debug port implementation-specific registers
3.18. Timestamp generator register summary
3.19. Timestamp generator register description
3.19.1. Counter Control Register, CNTCR
3.19.2. Counter Status Register, CNTSR
3.19.3. CNTFID0 Register
3.19.4. Peripheral ID4 Register
3.19.5. Peripheral ID5-7 registers
3.19.6. Peripheral ID0 Register
3.19.7. Peripheral ID1 Register
3.19.8. Peripheral ID2 Register
3.19.9. Peripheral ID3 Register
3.19.10. Component ID0 Register
3.19.11. Component ID1 Register
3.19.12. Component ID2 Register
3.19.13. Component ID3 Register
4. Debug Access Port
4.1. About the Debug Access Port
4.1.1. DAP flow of control
4.2. SWJ-DP
4.2.1. Structure of the SWJ-DP
4.2.2. Operation of the SWJ-DP mode
4.2.3. JTAG and SWD interface
4.2.4. Clock, reset, and power domain support
4.2.5. SWD and JTAG selection mechanism
4.3. DAPBUS interconnect interfaces
4.3.1. Clock and reset
4.3.2. Functional interfaces
4.3.3. Normal operating modes
4.4. DAP asynchronous bridge
4.4.1. Clock and reset
4.4.2. Functional interface
4.4.3. Functional description
4.4.4. Low-power support
4.5. DAP synchronous bridge
4.5.1. Clock and reset
4.5.2. Functional interface
4.5.3. Functional description
4.6. Common debug port features and registers
4.6.1. Features overview
4.6.2. Example pushed operations
4.7. Access ports
4.7.1. Overview
4.8. JTAG-AP
4.8.1. External interfaces
4.8.2. RTCK connections
4.9. AXI-AP
4.9.1. AXI-AP integration overview
4.9.2. Clock and reset
4.9.3. Functional interfaces
4.9.4. AXI-AP functionality
4.10. AHB-AP
4.10.1. External interfaces
4.10.2. Implementation features
4.10.3. DAP transfers
4.10.4. Differentiation between system and access port initiated error responses
4.10.5. Effects of resets
4.11. APB-AP
4.11.1. External interfaces
4.11.2. Implementation features
4.11.3. DAP transfers
4.12. APB Interconnect
4.12.1. Clock and reset
4.12.2. Functional interfaces
4.12.3. Device operation
4.13. APB asynchronous bridge
4.13.1. Clock and reset
4.13.2. Functional interface
4.13.3. Functional description
4.14. APB synchronous bridge
4.14.1. Clock and reset
4.14.2. Functional interface
4.14.3. Functional description
4.15. Auxiliary Access Port
4.16. Authentication requirements for Debug Access Port
4.17. Clocks, power, and resets
5. ATB Interconnect Components
5.1. ATB replicator
5.1.1. Clock and reset
5.1.2. Functional interfaces
5.1.3. Functional overview
5.2. ATB funnel
5.2.1. Clock and reset
5.2.2. Functional interface
5.2.3. Funnel functionality
5.2.4. Arbitration
5.2.5. Flushing
5.2.6. Syncreq propagation
5.2.7. Configuration
5.2.8. Cascaded funnel support
5.2.9. Unlocking funnel access
5.2.10. Claim scheme
5.2.11. Topology detection
5.2.12. Fixed configuration funnel
5.3. ATB upsizer
5.3.1. Clocks and reset
5.3.2. Functional interface
5.3.3. Component functionality
5.3.4. Flush
5.3.5. Syncreq propagation
5.4. ATB downsizer
5.4.1. Clocks and reset
5.4.2. Functional interface
5.4.3. Component functionality
5.4.4. Flush
5.4.5. Syncreq propagation
5.5. ATB asynchronous bridge
5.5.1. Functional interfaces
5.5.2. Clock and reset
5.5.3. Device operation
5.5.4. Low-power features
5.6. ATB synchronous bridge
5.6.1. Clock and reset
5.6.2. Functional interfaces
5.6.3. Operation
5.6.4. Syncreq
5.6.5. Low-power control
6. Timestamp Components
6.1. About the timestamp components
6.2. Timestamp solution
6.2.1. Timestamp generator
6.2.2. Timestamp encoder
6.2.3. Narrow timestamp replicator
6.2.4. Narrow timestamp asynchronous bridge
6.2.5. Narrow timestamp synchronous bridge
6.2.6. Timestamp decoder
6.2.7. Timestamp interpolator
7. Embedded Cross Trigger
7.1. About the ECT
7.1.1. How ECT works
7.1.2. CTI handshaking, synchronization, and clocks
7.2. ECT programmers model
7.3. ECT connectivity recommendations
7.4. ECT authentication requirements
7.4.1. Trigger inputs
7.4.2. Trigger outputs
7.4.3. ECT authentication signals
8. Trace Port Interface Unit
8.1. About the Trace Port Interface Unit
8.1.1. ATB interface
8.1.2. APB interface
8.2. Trace Out Port
8.3. Miscellaneous connections
8.4. TPIU trace port sizes
8.4.1. Programming registers
8.4.2. Omission of tracectl
8.5. TPIU triggers
8.5.1. Correlation with afvalid
8.6. Other TPIU design considerations
8.6.1. traceclk generation
8.6.2. tracectl removal
8.6.3. tracectl and tracedata multiplexing
8.6.4. Off-chip based traceclkin
8.7. Authentication requirements for TPIUs
8.8. TPIU pattern generator
8.8.1. Pattern generator modes of operation
8.8.2. Supported options
8.9. TPIU formatter and FIFO
8.9.1. Operational description
8.9.2. Special trace source IDs
8.9.3. Supported modes of operation
8.9.4. Periodic synchronization
8.10. Configuration options
8.10.1. Configuration guidelines
8.11. Example configuration scenarios
8.11.1. Capturing trace after an event and stopping
8.11.2. Only indicating triggers and still flushing
8.11.3. Multiple trigger indications
8.11.4. Independent triggering and flushing
9. Embedded Trace Buffer
9.1. About the ETB
9.1.1. ATB interface
9.1.2. ETB triggering and flushing ports
9.1.3. ETB status ports
9.1.4. Memory BIST interface
9.2. ETB clocks, resets, and synchronization
9.2.1. ETB clock domains
9.2.2. ETB resets
9.2.3. ETB synchronization
9.3. ETB trace capture and formatting
9.3.1. Formatter data processing
9.3.2. Special trace source IDs
9.3.3. Special modes of operation
9.3.4. Stopping trace
9.4. Flush assertion
9.5. Triggers
9.6. Write address generation for trace data storage
9.7. Trace data storage
9.8. APB configuration and RAM access
9.8.1. Read access
9.8.2. Write access
9.9. Trace RAM
9.10. Authentication requirements for CoreSight ETBs
9.11. ETB RAM support
9.11.1. Access sizes
9.11.2. BIST interface
9.11.3. RAM instantiation
10. Granular Power Requestor
10.1. Granular Power Requestor interfaces
10.1.1. Clock and reset
10.1.2. Functional interfaces
10.1.3. Device unlocking
A. Signal Descriptions
A.1. Debug Access Port signals
A.1.1. Serial wire or JTAG - Debug Port signals
A.1.2. DAP bus interconnect signals
A.1.3. DAP asynchronous bridge signals
A.1.4. DAP synchronous bridge signals
A.1.5. JTAG - Access Port signals
A.1.6. Advanced eXtensible Interface - Access Port signals
A.1.7. Advanced High-performance Bus - Access Port signals
A.1.8. Advanced Peripheral Bus - Access Port signals
A.1.9. APB interconnect signals
A.1.10. APB asynchronous bridge signals
A.1.11. APB synchronous bridge signals
A.2. Advanced Trace Bus interconnect signals
A.2.1. ATB replicator signals
A.2.2. ATB trace funnel signals
A.2.3. ATB upsizer signals
A.2.4. ATB downsizer signals
A.2.5. ATB asynchronous bridge signals
A.2.6. ATB synchronous bridge signals
A.3. Timestamp component signals
A.3.1. Timestamp generator signals
A.3.2. Timestamp encoder signals
A.3.3. Narrow timestamp replicator signals
A.3.4. Narrow timestamp asynchronous bridge signals
A.3.5. Narrow timestamp synchronous bridge signals
A.3.6. Timestamp decoder signals
A.3.7. Timestamp interpolator signals
A.4. Trigger component signals
A.4.1. Cross Trigger Interface signals
A.4.2. Cross Trigger Matrix signals
A.5. Trace sink signals
A.5.1. Trace Port Interface Unit signals
A.5.2. Embedded Trace Buffer signals
A.6. Authentication and event bridges
A.6.1. Authentication asynchronous bridge signals
A.6.2. Authentication synchronous bridge signals
A.6.3. Event asynchronous bridge signals
A.7. Granular power requestor signals
B. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. CoreSight debugging environment
2.1. SWJ - DP block diagram
2.2. DAPBUS interconnect block diagram
2.3. DAP asynchronous bridge block diagram
2.4. DAP synchronous bridge block diagram
2.5. JTAG-Access Port block diagram
2.6. Advanced eXtensible Interface - Access Port block diagram
2.7. Advanced High-performance Bus - Access Port block diagram
2.8. Advanced Peripheral Bus - Access Port block diagram
2.9. APB interconnect with ROM table block diagram
2.10. APB asynchronous bridge block diagram
2.11. APB synchronous bridge block diagram
2.12. ATB replicator block diagram
2.13. ATB funnel block diagram
2.14. ATB upsizer block diagram
2.15. ATB downsizer block diagram
2.16. ATB asynchronous bridge block diagram
2.17. ATB synchronous bridge block diagram
2.18. Timestamp generator block diagram
2.19. Timestamp encoder block diagram
2.20. Narrow timestamp replicator block diagram
2.21. Narrow timestamp asynchronous bridge block diagram
2.22. Narrow timestamp synchronous bridge block diagram
2.23. Timestamp decoder block diagram
2.24. Timestamp interpolator block diagram
2.25. Cross Trigger Interface block diagram
2.26. Cross Trigger Matrix block diagram
2.27. Trace Port Interface Unit block diagram
2.28. Embedded Trace Buffer block diagram
2.29. Authentication asynchronous bridge block diagram
2.30. Authentication synchronous bridge block diagram
2.31. Event asynchronous bridge block diagram
2.32. Granular Power Requestor block diagram
3.1. CPWRUPREQ Register bit assignments
3.2. CPWRUPACK Register bit assignments
3.3. ITCTRL Register bit assignments
3.4. CLAIMSET Register bit assignments
3.5. CLAIMCLR Register bit assignments
3.6. LAR bit assignments
3.7. LSR bit assignments
3.8. AUTHSTATUS Register bit assignments
3.9. DEVARCH Register bit assignments
3.10. DEVID Register bit assignments
3.11. DEVTYPE Register bit assignments
3.12. PIDR4 bit assignments
3.13. PIDR5-7 bit assignments
3.14. PIDR0 bit assignments
3.15. PIDR1 bit assignments
3.16. PIDR2 bit assignments
3.17. PIDR3 bit assignments
3.18. CIDR0 bit assignments
3.19. CIDR1 bit assignments
3.20. CIDR2 bit assignments
3.21. CIDR3 bit assignments
3.22. ROM_ENTRY_n Register bit assignments
3.23. PIDR4 bit assignments
3.24. PIDR5-7 bit assignments
3.25. PIDR0 bit assignments
3.26. PIDR1 bit assignments
3.27. PIDR2 bit assignments
3.28. PIDR3 bit assignments
3.29. CIDR0 bit assignments
3.30. CIDR1 bit assignments
3.31. CIDR2 bit assignments
3.32. CIDR3 bit assignments
3.33. Ctrl_Reg Register bit assignments
3.34. Priority_Ctrl_Reg Register bit assignments
3.35. ITATBDATA0 Register bit assignments
3.36. ITATBCTR2 Register bit assignments
3.37. ITATBCTR1 Register bit assignments
3.38. ITATBCTR0 Register bit assignments
3.39. ITCTRL Register bit assignments
3.40. CLAIMSET Register bit assignments
3.41. CLAIMCLR Register bit assignments
3.42. LAR bit assignments
3.43. LSR bit assignments
3.44. AUTHSTATUS Register bit assignments
3.45. DEVID Register bit assignments
3.46. DEVTYPE Register bit assignments
3.47. PIDR4 bit assignments
3.48. PIDR5-7 bit assignments
3.49. PIDR0 bit assignments
3.50. PIDR1 bit assignments
3.51. PIDR2 bit assignments
3.52. PIDR3 bit assignments
3.53. CIDR0 bit assignments
3.54. CIDR1 bit assignments
3.55. CIDR2 bit assignments
3.56. CIDR3 bit assignments
3.57. IDFILTER0 Register bit assignments
3.58. IDFILTER1 Register bit assignments
3.59. ITATBCTR0 Register bit assignments
3.60. ITATBCTR1 Register bit assignments
3.61. ITCTRL Register bit assignments
3.62. CLAIMSET Register bit assignments
3.63. CLAIMCLR Register bit assignments
3.64. LAR bit assignments
3.65. LSR bit assignments
3.66. AUTHSTATUS Register bit assignments
3.67. DEVID Register bit assignments
3.68. DEVTYPE Register bit assignments
3.69. PIDR4 bit assignments
3.70. PIDR5-7 bit assignments
3.71. PIDR0 bit assignments
3.72. PIDR1 bit assignments
3.73. PIDR2 bit assignments
3.74. PIDR3 bit assignments
3.75. CIDR0 bit assignments
3.76. CIDR1 bit assignments
3.77. CIDR2 bit assignments
3.78. CIDR3 bit assignments
3.79. RDP Register bit assignments
3.80. STS Register bit assignments
3.81. RRD Register bit assignments
3.82. RRP Register bit assignments
3.83. RWP Register bit assignments
3.84. TRG Register bit assignments
3.85. CTL Register bit assignments
3.86. RWD Register bit assignments
3.87. FFSR Register bit assignments
3.88. FFCR Register bit assignments
3.89. ITMISCOP0 Register bit assignments
3.90. ITTRFLINACK Register bit assignments
3.91. ITTRFLIN Register bit assignments
3.92. ITATBDATA0 Register bit assignments
3.93. ITATBCTR2 Register bit assignments
3.94. ITATBCTR1 Register bit assignments
3.95. ITATBCTR0 Register bit assignments
3.96. ITCTRL Register bit assignments
3.97. CLAIMSET Register bit assignments
3.98. CLAIMCLR Register bit assignments
3.99. LAR bit assignments
3.100. LSR bit assignments
3.101. AUTHSTATUS Register bit assignments
3.102. DEVID Register bit assignments
3.103. DEVTYPE Register bit assignments
3.104. PIDR4 bit assignments
3.105. PIDR5-7 bit assignments
3.106. PIDR0 bit assignments
3.107. PIDR1 bit assignments
3.108. PIDR2 bit assignments
3.109. PIDR3 bit assignments
3.110. CIDR0 bit assignments
3.111. CIDR1 bit assignments
3.112. CIDR2 bit assignments
3.113. CIDR3 bit assignments
3.114. CTICONTROL Register bit assignments
3.115. CTIINTACK Register bit assignments
3.116. CTIAPPSET Register bit assignments
3.117. CTIAPPCLEAR Register bit assignments
3.118. CTIAPPPULSE Register bit assignments
3.119. CTIINEN0 Register bit assignments
3.120. CTIINEN1 Register bit assignments
3.121. CTIINEN2 Register bit assignments
3.122. CTIINEN3 Register bit assignments
3.123. CTIINEN4 Register bit assignments
3.124. CTIINEN5 Register bit assignments
3.125. CTIINEN6 Register bit assignments
3.126. CTIINEN7 Register bit assignments
3.127. CTIOUTEN0 Register bit assignments
3.128. CTIOUTEN1 Register bit assignments
3.129. CTIOUTEN2 Register bit assignments
3.130. CTIOUTEN3 Register bit assignments
3.131. CTIOUTEN4 Register bit assignments
3.132. CTIOUTEN5 Register bit assignments
3.133. CTIOUTEN6 Register bit assignments
3.134. CTIOUTEN7 Register bit assignments
3.135. CTITRIGINSTATUS Register bit assignments
3.136. CTITRIGOUTSTATUS Register bit assignments
3.137. CTICHINSTATUS Register bit assignments
3.138. CTICHOUTSTATUS Register bit assignments
3.139. CTIGATE Register bit assignments
3.140. ASICCTL Register bit assignments
3.141. ITCHINACK Register bit assignments
3.142. ITTRIGINACK Register bit assignments
3.143. ITCHOUT Register bit assignments
3.144. ITTRIGOUT Register bit assignments
3.145. ITCHOUTACK Register bit assignments
3.146. ITTRIGOUTACK Register bit assignments
3.147. ITCHIN Register bit assignments
3.148. ITTRIGIN Register bit assignments
3.149. ITCTRL Register bit assignments
3.150. CLAIMSET Register bit assignments
3.151. CLAIMCLR Register bit assignments
3.152. LAR bit assignments
3.153. LSR bit assignments
3.154. AUTHSTATUS Register bit assignments
3.155. DEVID Register bit assignments
3.156. DEVTYPE Register bit assignments
3.157. PIDR4 bit assignments
3.158. PIDR5-7 bit assignments
3.159. PIDR0 bit assignments
3.160. PIDR1 bit assignments
3.161. PIDR2 bit assignments
3.162. PIDR3 bit assignments
3.163. CIDR0 bit assignments
3.164. CIDR1 bit assignments
3.165. CIDR2 bit assignments
3.166. CIDR3 bit assignments
3.167. Supported_Port_Sizes Register bit assignments
3.168. Current_port_size Register bit assignments
3.169. Supported_trigger_modes Register bit assignments
3.170. Trigger_counter_value Register bit assignments
3.171. Trigger_multiplier Register bit assignments
3.172. Supported_test_pattern_modes Register bit assignments
3.173. Current_test_pattern_mode Register bit assignments
3.174. TPRCR Register bit assignments
3.175. FFSR Register bit assignments
3.176. FFCR Register bit assignments
3.177. FSCR Register bit assignments
3.178. EXTCTL_In_Port Register bit assignments
3.179. EXTCTL_Out_Port Register bit assignments
3.180. ITTRFLINACK Register bit assignments
3.181. ITTRFLIN Register bit assignments
3.182. ITATBDATA0 Register bit assignments
3.183. ITATBCTR2 Register bit assignments
3.184. ITATBCTR1 Register bit assignments
3.185. ITATBCTR0 Register bit assignments
3.186. ITCTRL Register bit assignments
3.187. CLAIMSET Register bit assignments
3.188. CLAIMCLR Register bit assignments
3.189. LAR Register bit assignments
3.190. LSR bit assignments
3.191. AUTHSTATUS Register bit assignments
3.192. DEVID Register bit assignments
3.193. DEVTYPE Register bit assignments
3.194. PIDR4 bit assignments
3.195. PIDR5-7 bit assignments
3.196. PIDR0 bit assignments
3.197. PIDR1 bit assignments
3.198. PIDR2 bit assignments
3.199. PIDR3 bit assignments
3.200. CIDR0 bit assignments
3.201. CIDR1 bit assignments
3.202. CIDR2 bit assignments
3.203. CIDR3 bit assignments
3.204. JTAG-AP CSW Register bit assignments
3.205. JTAG-AP Port Select Register bit assignments
3.206. JTAG-AP Port Status Register bit assignments
3.207. JTAG-AP Identification Register bit assignments
3.208. AHB-AP CSW Register bit assignments
3.209. AHB-AP Identification Register bit assignments
3.210. AXI-AP CSW Register bit assignments
3.211. AXI-AP Transfer Address Register bit assignments
3.212. AXI-AP Data RW Register bit assignments
3.213. AXI-AP Banked DATA Register bit assignments
3.214. ACE Barrier Transaction Register bit assignments
3.215. AXI-AP Debug Base Address Register bit assignments
3.216. AXI-AP Configuration Register bit assignments
3.217. AXI-AP Identification Register bit assignments
3.218. APB-AP Control/Status Word Register bit assignments
3.219. APB-AP Transfer Address Register bit assignments
3.220. Debug APB ROM Address Register bit assignments
3.221. APB-AP Identification Register bit assignments
3.222. JTAG-DP AP Abort Register bit assignments
3.223. SW-DP AP Abort Register bit assignments
3.224. Identification Code Register bit assignments
3.225. Control/Status Register bit assignments
3.226. AP Select Register bit assignments
3.227. Wire Control Register bit assignments
3.228. Target Identification Register bit assignments
3.229. Data Link Protocol Identification Register bit assignments
3.230. CNTCR Register bit assignments
3.231. CNTSR Register bit assignments
3.232. CNTFID0 Register bit assignments
3.233. PIDR4 bit assignments
3.234. PIDR5-7 bit assignments
3.235. PIDR0 bit assignments
3.236. PIDR1 bit assignments
3.237. PIDR2 bit assignments
3.238. PIDR3 bit assignments
3.239. CIDR0 bit assignments
3.240. CIDR1 bit assignments
3.241. CIDR2 bit assignments
3.242. CIDR3 bit assignments
4.1. Structure of the CoreSight DAP components
4.2. SWJ-DP
4.3. AXI-AP
4.4. AHB-AP
4.5. APB Access Port
4.6. DAP flow of control
4.7. SW-DP to DAP bus timing for write
4.8. SW-DP to DAP bus timing for read
4.9. SW-DP idle timing
4.10. AXI-AP example integration with CoreSight SoC DAP
5.1. Example ATB replicator
5.2. ATB funnel minimum hold time example
5.3. ATB funnel arbitration example
5.4. ATB funnel example flushing waveform
5.5. Upsizer example waveform
5.6. Example flushing waveform
5.7. Downsizer example waveform
5.8. Downsizer example flushing waveform
5.9. ATB asynchronous bridge normal operation for input
5.10. ATB asynchronous bridge normal operation for output
5.11. ATB asynchronous bridge flushing behavior
5.12. ATB asynchronous bridge flushing operation during powerdown request
6.1. Timestamp example system
6.2. Write access to enable counter and read access
6.3. Counter operation
6.4. Low-power entry and exit timing diagram
6.5. Low-power entry and exit timing diagram
7.1. CoreSight CTI and CTM block diagram
7.2. Channel interface handshaking
8.1. TPIU block diagram
8.2. Externally derived traceclk
8.3. Construction of formatter data packets
8.4. Capturing trace after an event and stopping
8.5. Multiple trigger indications from flushes
8.6. Independent triggering during repeated flushes
9.1. ETB block diagram
9.2. Construction of data packets within the formatter
9.3. ETB trace RAM block wrapper

List of Tables

1. Typographical conventions
1.1. CoreSight block summary
3.1. GPR register summary
3.2. CPWRUPREQ Register bit assignments
3.3. CPWRUPACK Register bit assignments
3.4. ITCTRL Register bit assignments
3.5. CLAIMSET Register bit assignments
3.6. CLAIMCLR Register bit assignments
3.7. LAR bit assignments
3.8. LSR bit assignments
3.9. AUTHSTATUS Register bit assignments
3.10. DEVARCH Register bit assignments
3.11. DEVID Register bit assignments
3.12. DEVTYPE Register bit assignments
3.13. PIDR4 bit assignments
3.14. PIDR5-7 bit assignments
3.15. PIDR0 bit assignments
3.16. PIDR1 bit assignments
3.17. PIDR2 bit assignments
3.18. PIDR3 bit assignments
3.19. CIDR0 bit assignments
3.20. CIDR1 bit assignments
3.21. CIDR2 bit assignments
3.22. CIDR3 bit assignments
3.23. APB interconnect register summary
3.24. ROM_ENTRY_n Register bit assignments
3.25. PIDR4 bit assignments
3.26. PIDR5-7 bit assignments
3.27. PIDR0 bit assignments
3.28. PIDR1 bit assignments
3.29. PIDR2 bit assignments
3.30. PIDR3 bit assignments
3.31. CIDR0 bit assignments
3.32. CIDR1 bit assignments
3.33. CIDR2 bit assignments
3.34. CIDR3 bit assignments
3.35. ATB funnel register summary
3.36. Ctrl_Reg Register bit assignments
3.37. Priority_Ctrl_Reg Register bit assignments
3.38. ITATBDATA0 Register bit assignments
3.39. ITATBCTR2 Register bit assignments
3.40. ITATBCTR1 Register bit assignments
3.41. ITATBCTR0 Register bit assignments
3.42. ITCTRL Register bit assignments
3.43. CLAIMSET Register bit assignments
3.44. CLAIMCLR Register bit assignments
3.45. LAR bit assignments
3.46. LSR bit assignments
3.47. AUTHSTATUS Register bit assignments
3.48. DEVID Register bit assignments
3.49. DEVTYPE Register bit assignments
3.50. PIDR4 bit assignments
3.51. PIDR5-7 bit assignments
3.52. PIDR0 bit assignments
3.53. PIDR1 bit assignments
3.54. PIDR2 bit assignments
3.55. PIDR3 bit assignments
3.56. CIDR0 bit assignments
3.57. CIDR1 bit assignments
3.58. CIDR2 bit assignments
3.59. CIDR3 bit assignments
3.60. ATB replicator register summary
3.61. IDFILTER0 Register bit assignments
3.62. IDFILTER1 Register bit assignments
3.63. ITATBCTR0 Register bit assignments
3.64. ITATBCTR1 Register bit assignments
3.65. ITCTRL Register bit assignments
3.66. CLAIMSET Register bit assignments
3.67. CLAIMCLR Register bit assignments
3.68. LAR bit assignments
3.69. LSR bit assignments
3.70. AUTHSTATUS Register bit assignments
3.71. DEVID Register bit assignments
3.72. DEVTYPE Register bit assignments
3.73. PIDR4 bit assignments
3.74. PIDR5-7 bit assignments
3.75. PIDR0 bit assignments
3.76. PIDR1 bit assignments
3.77. PIDR2 bit assignments
3.78. PIDR3 bit assignments
3.79. CIDR0 bit assignments
3.80. CIDR1 bit assignments
3.81. CIDR2 bit assignments
3.82. CIDR3 bit assignments
3.83. ETB register summary
3.84. RDP Register bit assignments
3.85. STS Register bit assignments
3.86. RRD Register bit assignments
3.87. RRP Register bit assignments
3.88. RWP Register bit assignments
3.89. TRG Register bit assignments
3.90. CTL Register bit assignments
3.91. RWD Register bit assignments
3.92. FFSR Register bit assignments
3.93. FFCR Register bit assignments
3.94. ITMISCOP0 Register bit assignments
3.95. ITTRFLINACK Register bit assignments
3.96. ITTRFLIN Register bit assignments
3.97. ITATBDATA0 Register bit assignments
3.98. ITATBCTR2 Register bit assignments
3.99. ITATBCTR1 Register bit assignments
3.100. ITATBCTR0 Register bit assignments
3.101. ITCTRL Register bit assignments
3.102. CLAIMSET Register bit assignments
3.103. CLAIMCLR Register bit assignments
3.104. LAR bit assignments
3.105. LSR bit assignments
3.106. AUTHSTATUS Register bit assignments
3.107. DEVID Register bit assignments
3.108. DEVTYPE Register bit assignments
3.109. PIDR4 bit assignments
3.110. PIDR5-7 bit assignments
3.111. PIDR0 bit assignments
3.112. PIDR1 bit assignments
3.113. PIDR2 bit assignments
3.114. PIDR3 bit assignments
3.115. CIDR0 bit assignments
3.116. CIDR1 bit assignments
3.117. CIDR2 bit assignments
3.118. CIDR3 bit assignments
3.119. CTI register summary
3.120. CTICONTROL Register bit assignments
3.121. CTIINTACK Register bit assignments
3.122. CTIAPPSET Register bit assignments
3.123. CTIAPPCLEAR Register bit assignments
3.124. CTIAPPPULSE Register bit assignments
3.125. CTIINEN0 Register bit assignments
3.126. CTIINEN1 Register bit assignments
3.127. CTIINEN2 Register bit assignments
3.128. CTIINEN3 Register bit assignments
3.129. CTIINEN4 Register bit assignments
3.130. CTIINEN5 Register bit assignments
3.131. CTIINEN6 Register bit assignments
3.132. CTIINEN7 Register bit assignments
3.133. CTIOUTEN0 Register bit assignments
3.134. CTIOUTEN1 Register bit assignments
3.135. CTIOUTEN2 Register bit assignments
3.136. CTIOUTEN3 Register bit assignments
3.137. CTIOUTEN4 Register bit assignments
3.138. CTIOUTEN5 Register bit assignments
3.139. CTIOUTEN6 Register bit assignments
3.140. CTIOUTEN7 Register bit assignments
3.141. CTITRIGINSTATUS Register bit assignments
3.142. CTITRIGOUTSTATUS Register bit assignments
3.143. CTICHINSTATUS Register bit assignments
3.144. CTICHOUTSTATUS Register bit assignments
3.145. CTIGATE Register bit assignments
3.146. ASICCTL Register bit assignments
3.147. ITCHINACK Register bit assignments
3.148. ITTRIGINACK Register bit assignments
3.149. ITCHOUT Register bit assignments
3.150. ITTRIGOUT Register bit assignments
3.151. ITCHOUTACK Register bit assignments
3.152. ITTRIGOUTACK Register bit assignments
3.153. ITCHIN Register bit assignments
3.154. ITTRIGIN Register bit assignments
3.155. ITCTRL Register bit assignments
3.156. CLAIMSET Register bit assignments
3.157. CLAIMCLR Register bit assignments
3.158. LAR bit assignments
3.159. LSR bit assignments
3.160. AUTHSTATUS Register bit assignments
3.161. DEVID Register bit assignments
3.162. DEVTYPE Register bit assignments
3.163. PIDR4 bit assignments
3.164. PIDR5-7 bit assignments
3.165. PIDR0 bit assignments
3.166. PIDR1 bit assignments
3.167. PIDR2 bit assignments
3.168. PIDR3 bit assignments
3.169. CIDR0 bit assignments
3.170. CIDR1 bit assignments
3.171. CIDR2 bit assignments
3.172. CIDR3 bit assignments
3.173. TPIU register summary
3.174. Supported_Port_Sizes Register bit assignments
3.175. Current_port_size Register bit assignments
3.176. Supported_trigger_modes Register bit assignments
3.177. Trigger_counter_value Register bit assignments
3.178. Trigger_multiplier Register bit assignments
3.179. Supported_test_pattern_modes Register bit assignments
3.180. Current_test_pattern_mode Register bit assignments
3.181. TPRCR Register bit assignments
3.182. FFSR Register bit assignments
3.183. FFCR Register bit assignments
3.184. FSCR Register bit assignments
3.185. EXTCTL_In_Port Register bit assignments
3.186. EXTCTL_Out_Port Register bit assignments
3.187. ITTRFLINACK Register bit assignments
3.188. ITTRFLIN Register bit assignments
3.189. ITATBDATA0 Register bit assignments
3.190. ITATBCTR2 Register bit assignments
3.191. ITATBCTR1 Register bit assignments
3.192. ITATBCTR0 Register bit assignments
3.193. ITCTRL Register bit assignments
3.194. CLAIMSET Register bit assignments
3.195. CLAIMCLR Register bit assignments
3.196. LAR bit assignments
3.197. LSR bit assignments
3.198. AUTHSTATUS Register bit assignments
3.199. DEVID Register bit assignments
3.200. DEVTYPE Register bit assignments
3.201. PIDR4 bit assignments
3.202. PIDR5-7 bit assignments
3.203. PIDR0 bit assignments
3.204. PIDR1 bit assignments
3.205. PIDR2 bit assignments
3.206. PIDR3 bit assignments
3.207. CIDR0 bit assignments
3.208. CIDR1 bit assignments
3.209. CIDR2 bit assignments
3.210. CIDR3 bit assignments
3.211. JTAG-AP register summary
3.212. AHB-AP register summary
3.213. AXI-AP register summary
3.214. APB-AP register summary
3.215. Debug port register summary
3.216. JTAG-DP register summary
3.217. JTAG-AP CSW Register bit assignments
3.218. JTAG-AP Port Select Register bit assignments
3.219. JTAG-AP Port Status Register bit assignments
3.220. JTAG-AP Identification Register bit assignments
3.221. AHB-AP Control/Status Word Register bit assignments
3.222. AHB-AP Transfer Address Register bit assignments
3.223. AHB-AP Data Read/Write Register bit assignments
3.224. Banked Data Register bit assignments
3.225. ROM Address Register bit assignments
3.226. AHB-AP Identification Register bit assignments
3.227. AXI-AP CSW Register bit assignments
3.228. AXI-AP Transfer Address Register bit assignments
3.229. AXI-AP Data RW Register bit assignments
3.230. AXI-AP Banked Data Registers bit assignments
3.231. ACE Barrier Transaction Register bit assignments
3.232. AXI-AP Debug Base Address Register bit assignments
3.233. AXI-AP Configuration Register bit assignments
3.234. AXI-AP Identification Register bit assignments
3.235. APB Control/Status Word Register bit assignments
3.236. APB-AP Transfer Address Register bit assignments
3.237. ABP-AP Data Read/Write Register bit assignments
3.238. APB-AP Banked Data Registers bit assignments
3.239. Debug APB ROM Address Register bit assignments
3.240. APB-AP Identification Register bit assignments
3.241. AP Abort Register bit assignments
3.242. Identification Code Register bit assignments
3.243. JEDEC JEP-106 manufacturer ID code, with ARM values
3.244. Control/Status Register bit assignments
3.245. AP Select Register bit assignments
3.246. Wire Control Register bit assignments
3.247. Turnaround tristate period field bit definitions
3.248. Wire operating mode bit definitions
3.249. Target Identification Register bit assignments
3.250. Data Link Protocol Identification Register bit assignments
3.251. Timestamp generator register summary
3.252. CNTCR Register bit assignments
3.253. CNTSR Register bit assignments
3.254. CNTFID0 Register bit assignments
3.255. PIDR4 bit assignments
3.256. PIDR5-7 bit assignments
3.257. PIDR0 bit assignments
3.258. PIDR1 bit assignments
3.259. PIDR2 bit assignments
3.260. PIDR3 bit assignments
3.261. CIDR0 bit assignments
3.262. CIDR1 bit assignments
3.263. CIDR2 bit assignments
3.264. CIDR3 bit assignments
4.1. JTAG-DP physical interface
4.2. Terms used in SW-DP timing
4.3. TARGETID input connections
4.4. TARGETID mapping
4.5. JTAG to slave device signals
4.6. Difference between AXI and AP initiated error response
4.7. AXI-AP features at a glance
4.8. Valid combination of AxCACHE and AxDOMAIN values
4.9. Other AHB-AP ports
4.10. Example generation of byte lane strobes
4.11. Error responses with DAPSLVERR HIGH and TrInProg LOW
4.12. APB-AP other ports
4.13. Address width on master interfaces
5.1. Event sequence
5.2. Event sequence
5.3. Event sequence
5.4. Upsizer example description
5.5. Example flushing waveform
5.6. Downsizer example waveform
5.7. Example flushing waveform
5.8. Event sequence for input example
5.9. Event sequence for output example
5.10. Event sequence of the ATB asynchronous bridge flush operation
5.11. Event sequence of the ATB asynchronous bridge flushing operation during powerdown request
6.1. Event sequence of the write access to enable counter and read access
6.2. Event sequence of the counter operation
6.3. Event sequence of the low-power entry and exit timing diagram
6.4. Event sequence of the low-power entry and exit timing diagram
7.1. Event sequence of the channel interface handshaking
7.2. ECT recommended trigger outputs
7.3. ECT authentication signals
8.1. Trace Out Port signals
8.2. TPIU miscellaneous ports
8.3. Example Trace Out Port sizes
8.4. CoreSight representation of triggers
9.1. ETB triggering and flushing ports
9.2. ETB status ports
9.3. ETB Memory BIST interface ports
A.1. Serial wire and JTAG debug port signals
A.2. DAP bus interconnect signals
A.3. DAP asynchronous bridge signals
A.4. DAP synchronous bridge signals
A.5. DAP JTAG access port signals
A.6. DAP AXI access port signals
A.7. DAP AHB access port signals
A.8. APB access port signals
A.9. APB interconnect signals
A.10. APB asynchronous bridge signals
A.11. APB synchronous bridge signals
A.12. ATB replicator signals
A.13. ATB trace funnel signals
A.14. ATB upsizer signals
A.15. ATB downsizer signals
A.16. ATB asynchronous bridge signals
A.17. ATB synchronous bridge signals
A.18. Timestamp generator signals
A.19. Timestamp encoder signals
A.20. Narrow timestamp replicator signals
A.21. Narrow timestamp asynchronous bridge signals
A.22. Narrow timestamp synchronous bridge signals
A.23. Timestamp decoder signals
A.24. Timestamp interpolator signals
A.25. CTI signals
A.26. CTM signals
A.27. TPIU signals
A.28. ETB signals
A.29. Authentication asynchronous bridge signals
A.30. Authentication synchronous bridge signals
A.31. Event asynchronous bridge signals
A.32. Granular power requestor signals
B.1. Issue A
B.2. Differences between Issue A and Issue B
B.3. Differences between Issue B and Issue C
B.4. Differences between Issue C and Issue D

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A04 November 2011First release for r0p0.
Revision B16 April 2012First release for r1p0.
Revision C27 September 2012First release for r2p0.
Revision D14 December 2012First release for r2p1.
Copyright © 2011, 2012 ARM. All rights reserved.ARM DDI 0480D
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