A.4.1. Timestamp generator signals

Table A.21 shows the timestamp generator signals.

Table A.21. Timestamp generator signals

NameTypeClock domainDescription
clk InputclkAPB clock.
resetnInputclkAPB reset.
hltdbgInputclkRequest to halt the counter when the processor is in debug state.
paddrctrl[11:2]InputclkAPB address.
pselctrlInputclkAPB select. Indicates that the slave interface is selected and a data transfer is required.
penablectrlInputclkAPB enable. Indicates the second and subsequent cycles of a transfer initiated on a slave interface.
pwritectrlInputclkAPB RW transfer. Indicates an APB write access when HIGH and an APB read access when LOW.
pwdatactrl[31:0]InputclkAPB write data. This bus is driven by the APB master device connected to slave interface.
paddrread[11:2]InputclkAPB address.
pselreadInputclkAPB select. Indicates that the slave interface is selected and a data transfer is required.
penablereadInputclkAPB enable. Indicates the second and subsequent cycles of a transfer initiated on a slave interface.
pwritereadInputclkAPB RW transfer. Indicates an APB write access when HIGH and an APB read access when LOW. Because this is an RO interface, writes have no effect.
pwdataread[31:0]InputclkAPB write data. The APB master device connected to slave interface drives this bus. Because this is an RO interface, writes have no effect.

tsvalueb[63:0]

OutputclkWide timestamp value in binary.
tsforcesyncOutputclkResynchronization request.
preadyctrlOutputclkAPB ready. The slave device uses this signal to extend an APB transfer.
pslverrctrlOutputclkIndicates a transfer failure.
prdatactrl[31:0]OutputclkAPB read data. The slave interface drives this bus during read cycles.
preadyreadOutputclkAPB ready. The slave device uses this signal to extend an APB transfer.
pslverrreadOutputclkIndicates a transfer failure.
prdataread[31:0]OutputclkAPB read data. Slave interface drives this bus during read cycles.

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