A.1.4. DAPBUS synchronous bridge signals

Table A.5 shows the DAPBUS synchronous bridge signals.

Table A.5. DAPBUS synchronous bridge signals

Signal

Type

Clock domain

Description

dapclk

Input

dapclkThe DAP clock.

dapresetn

Input

dapclkThe DAP reset.
dapclkensInputdapclkThe DAP clock enable.
dapselsInputdapclkThe DAP select. Indicates that the slave device is selected and a data transfer is required.
dapabortsInputdapclkThe DAP abort. When this signal is asserted HIGH, then the DAP slave aborts the current DAP transfer and asserts dapreadys HIGH in the next cycle.
dapenablesInputdapclkThe DAP enable. Indicates the second and subsequent cycles of a DAP transfer
dapwritesInputdapclkThe DAP RW. Indicates a DAP write access when HIGH and a DAP read access when LOW.
dapaddrs[31:0]InputdapclkThe DAP address bus from master.
dapwdatas[31:0]InputdapclkThe DAP write data. The DAP master drives this bus.
dapclkenmInputdapclkThe DAP clock enable.
dapreadymInputdapclkThe DAP ready. The slave indicates whether it has completed the current transfer and is ready for the next transfer.
dapslverrmInputdapclkThe DAP slave error. The slave indicates that the present transfer has an error.
daprdatam[31:0]InputdapclkThe DAP read data. The read data of the present DAP read transfer.
csysreqInputdapclkClock powerdown request.
dapreadysOutputdapclkThe DAP slave ready. When asserted HIGH, it indicates that the slave completed the present DAP transfer and is ready for the next transfer.
dapslverrsOutputdapclkThe DAP slave error. Indicates that the present DAP transaction has an error.
daprdatas[31:0]OutputdapclkThe DAP read data. Carries the read data of a DAP read transfer.
dapselmOutputdapclkThe DAP select. Indicates that the master is selecting a particular slave for RW transfer.
dapabortmOutputdapclkThe DAP master abort. When asserted HIGH, it indicates that the master is aborting the current transaction.
dapenablemOutputdapclkThe DAP enable. Indicates the second and subsequent cycles of a DAP transfer.
dapwritemOutputdapclkThe DAP RW. Indicates a write transfer when HIGH and a read transfer when LOW.
dapaddrm[31:0]OutputdapclkThe DAP address bus.
dapwdatam[31:0]OutputdapclkThe DAP write data. The master drives this bus and carries the write data for the current write transfer.
csysackOutputdapclkClock powerdown acknowledge.
cactiveOutputdapclkClock is required when driven HIGH.

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