A.3.4. ATB downsizer signals

Table A.17 shows the ATB downsizer signals.

Table A.17. ATB downsizer signals

Signal

Type

Clock domain

Description

clk

Input

clkGlobal ATB clock.

resetn

Input

clk

The ATB interface reset. When LOW, this signal is asserted LOW asynchronously, and deasserted HIGH synchronously.

atvalidsInputclkA transfer is valid during this cycle. If LOW, all the other ATB signals must be ignored in this cycle.

atids[6:0]

Input

clkAn ID that uniquely identifies the source of the trace.

atbytess[sbw:0][a]

Input

clkThe number of bytes on atdata to be captured, minus 1.

atdatas[sdw-1:0][b]

Input

clkTrace data bus.

afreadys

Input

clkThis is a flush acknowledge. Asserted when buffers are flushed.

atreadym

Input

clkSlave is ready to accept data.

afvalidm

Input

clkThis is the flush signal. All buffers must be flushed because trace capture is about to stop.
syncreqmInputclkSynchronization request.

atreadys

Output

clkSlave is ready to accept data.

afvalids

Output

clkThis is the flush signal. All buffers must be flushed because trace capture is about to stop.
syncreqsOutputclkSynchronization request.
atvalidmOutputclkA transfer is valid during this cycle. If LOW, all other ATB signals must be ignored in this cycle.

atidm[6:0]

Output

clkAn ID that uniquely identifies the source of the trace.

atbytesm[mbw:0][c]

Output

clkThe number of bytes on ATDATA to be captured, minus 1.

atdatam[mdw:0][d]

Output

clkTrace data bus.

afreadym

Output

clkThis is a flush acknowledge. Asserted when buffers are flushed.

[a] Where sbw can have the range 0-3 and is automatically calculated at configuration time based on the data width of the slave interface.

[b] Where sdw is the data width of the slave interface.

[c] Where mbw can have the range 0-3 and is automatically calculated at configuration time based on the data width of the master interface.

[d] Where mdw is the data width of the master interface.


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