Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Issue A

ChangeLocationAffects
First release--

Table B.2. Differences between Issue A and Issue B

ChangeLocationAffects
Correction to signal name capitalization and signal directions.Chapter 2 Functional OverviewAll revisions
Correction to signal name capitalization and signal directions.Appendix A Signal DescriptionsAll revisions
Clarification of management register description.Chapter 3 Programmers ModelAll revisions
Component revision updated in the identification registers.Chapter 3 Programmers Modelr1p0
ATB replicator IDFILTER0 diagram updated.Figure 3.52All revisions
Moved and updated DAPBUS interconnect and APB interconnect and ROM table chapters into subsections of the Debug Access Port.Chapter 4 Debug Access PortAll revisions
Component versions updated in block summary.CoreSight SoC-400 block summaryr1p0 and above
Detail added on clock domain crossing bridges.Chapter 4 Debug Access PortAll revisions
Detail added on clock domain crossing bridges.Chapter 6 ATB Interconnect ComponentsAll revisions
Detail added on clock domain crossing bridges.Chapter 7 Timestamp ComponentsAll revisions
Event Asynchronous Bridge component information included.Entire documentAll revisions
Granular Power Requestor component added and referenced in Granular Power Requestor and Granular power requestor signals.Chapter 11 Granular Power Requestorr1p0 and above
Timestamp interpolator component added and referenced in Timestamp interpolator and Timestamp interpolator signals.Timestamp interpolatorr1p0 and above

Table B.3. Differences between Issue B and Issue C

ChangeLocationAffects
Updated Structure of CoreSight SoC-400 section.Chapter 1 IntroductionAll revisions
Updated Narrow timestamp asynchronous bridge revision in CoreSight SoC-400 block summary.Chapter 1 IntroductionAll revisions
Updated Product revisions for r2p0.Chapter 1 Introductionr2p0
Added rombaseaddrl[31:0] and rombaseaddru[31:0] to Figure 2.6.Chapter 2 Functional OverviewAll revisions
Added rombaseaddr[31:0] to Figure 2.7.Chapter 2 Functional OverviewAll revisions
Updated Event asynchronous bridge section.Chapter 2 Functional OverviewAll revisions
Moved and updated JTAG-DP register summary into subsection of the Debug port register summary. Chapter 3 Programmers ModelAll revisions
Moved and updated JTAP-DP register descriptions into subsection of the Debug port implementation-specific registers. Chapter 3 Programmers ModelAll revisions
Reset value correction in JTAG-DP register summary.Chapter 3 Programmers ModelAll revisions
Updated the description in Table 3.218.Chapter 3 Programmers ModelAll revisions
Updated the description in Table 3.229.Chapter 3 Programmers ModelAll revisions
Component revision updated in the identification registers.Chapter 3 Programmers Modelr2p0
Updated DAP flow of control section.Chapter 4 Debug Access PortAll revisions
Moved and updated Operation in JTAG-DP mode and Operation in SW-DP mode into subsection of the JTAG and SWD interface. Chapter 4 Debug Access PortAll revisions
Updated ATB upsizer section.Chapter 6 ATB Interconnect ComponentsAll revisions
Updated Arbitration section in ATB funnel.Chapter 6 ATB Interconnect ComponentsAll revisions
Added rombaseaddrl[31:0] and rombaseaddru[31:0] to Table A.7.Appendix A Signal DescriptionsAll revisions
Added rombaseaddr[31:0] to Table A.8.Appendix A Signal DescriptionsAll revisions

Table B.4. Differences between Issue C and Issue D

ChangeLocationAffects

Updated the signal case for the following block diagrams:

Chapter 2 Functional OverviewAll
Updated the offset value for CIDR 0-3 in Table 3.246Chapter 3 Programmers ModelAll
Updated the top-level signal case for ECT components.

Chapter 8 Embedded Cross Trigger

All
Updated the top-level signal case for TPIU components.Chapter 9 Trace Port Interface UnitAll
Updated the top-level signal case for ETB components.Chapter 10 Embedded Trace BufferAll
Updated the top-level signal case for ECT, TPIU, and ETB components.Appendix A Signal DescriptionsAll
Updated the component version references

Table 1.1

Table 3.51

All

Table B.5. Differences between Issue D and Issue E

Change

Location

Affects

Updated product name to CoreSight SoC-400Entire document

All

Added compliance information

Compliance

All

Updated signalsFigure 2.6

All

Updated Debug Base Register descriptionsAll
Updated reset value for DOMAIN fieldAXI-AP Control/Status Word registerr3p0
Updated figure to show JTAG-DPFigure 3.217All
Modified the revision value in AHB-AP Identification registerTable 3.219r3p0
Added a note for Domain field in AXI-AP CSW registerTable 3.220r3p0
Updated ARLOCK and AWLOCK sizesAXI transfersAll
Added synchronization request signals

All


Table B.6. Differences between Issue E and Issue F

ChangeLocationAffects
Corrected case of signals.ThroughoutAll
Updated the component block versions.

Chapter 1 Introduction

Chapter 3 Programmers Model

r3p1
Updated the example CoreSight SoC-400 system.

Typical CoreSight SoC-400 system

All
Improved clarity of the introduction.

Chapter 1 Introduction

All
Improved clarity of component descriptions in the functional overview, and redistributed information between this document, the ARM® CoreSight™ SoC-400 Integration Manual, and the ARM® CoreSight™ SoC-400 Implementation Guide to better match the intended audience of each document.

Chapter 2 Functional Overview

All
Moved APB component descriptions from DAP component descriptions to their own sections and chapter.

Chapter 2 Functional Overview

Chapter 4 Debug Access Port

Chapter 5 APB Interconnect Components

Appendix A Signal Descriptions

All
Moved event asynchronous bridge description from authentication bridges to cross-triggering components.

Chapter 2 Functional Overview

Chapter 8 Embedded Cross Trigger

Appendix A Signal Descriptions

All
Changed dapaddr[7:2] to dapcaddr[7:2].

AXI access port

Table A.7

r3p1
Removed ts_bit_valid_qualify signal from narrow timestamp replicator.

Narrow timestamp replicator

Narrow timestamp replicator

Table A.23

r3p1
Corrected timestamp interpolator signal list.

Timestamp interpolator

Table A.28

All
Added description of the authentication replicator.

Authentication bridges

Authentication and event bridges

All
Improved clarity of various programmers model registers.Chapter 3 Programmers ModelAll
Replaced SW-DP description of IDCODE register with DPIDR Register.Debug port implementation-specific registersAll
Renamed SW-DP WCR Register to DLCR Register.Debug port implementation-specific registersAll
Added description of Timestamp generator CNTCVL and CNTCVU registers.

Timestamp generator registers description

All
Reorganized, consolidated and rewrote substantial information in the component description chapters to improve clarity.

Chapter 4 Debug Access Port

Chapter 5 APB Interconnect Components

Chapter 6 ATB Interconnect Components

Chapter 7 Timestamp Components

Chapter 8 Embedded Cross Trigger

Chapter 9 Trace Port Interface Unit

Chapter 10 Embedded Trace Buffer

All

Added and corrected information on clocks and resets for each component.

Described where synchronizers are required.

Added note to consult the ARM® CoreSight™ SoC-400 Integration Manual, when using clock enables to interface between synchronous clock domains.

Chapter 4 Debug Access Port

Chapter 5 APB Interconnect Components

Chapter 6 ATB Interconnect Components

Chapter 7 Timestamp Components

Chapter 8 Embedded Cross Trigger

Chapter 9 Trace Port Interface Unit

Chapter 10 Embedded Trace Buffer

All
Clarified the behavior of low power interfaces.

Chapter 5 APB Interconnect Components

Chapter 6 ATB Interconnect Components

Chapter 7 Timestamp Components

All
Renamed SProt to CSW.Prot[1], because SProt is not defined elsewhere.

Chapter 4 Debug Access Port

Chapter 5 APB Interconnect Components

Chapter 6 ATB Interconnect Components

All
Corrected arbitration behavior of the non-programmable funnel.Non-programmable funnelAll
Described use of ATB synchronous bridge as a trace buffer.ATB synchronous bridgeAll
Described usage of the timestamp distribution network for processor time and CoreSight time, and clarified that the same network must not be used for both.Chapter 7 Timestamp ComponentsAll
Clarified usage of the timestamp generator hltdbg signal.Timestamp generatorAll
Updated guidance to TPA designers on traceclk alignment expectations.traceclk alignmentAll
Added flowcharts from CoreSight Design Kits explaining ETB trace stop, flush, and trigger operation.ETB trace capture and formattingAll
Removed Granular Power Requestor chapter from the book, because the information is provided in Granular Power Requestor and other sections.Chapter 2 Functional OverviewAll
Corrected CTM signal list to show that its channel interfaces are always four channels wide.Table A.30All
Listed signals that must be connected between slave and master interface components of asynchronous bridges when separately implemented Appendix A Signal DescriptionsAll

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