The timestamp components generate and distribute a consistent time value to multiple processors and other IP in a SoC. Figure 7.1 shows an example timestamp system.

The timestamp interconnect provides a mechanism for efficiently distributing a timestamp value across a potentially large system in a way that is cost-effective to implement. It has the following features:

The interconnect ensures that any components that uses the distributed timestamp are synchronized to the distributed count value with minimal skew while the timestamp interconnect is clocked. When a portion of the timestamp interconnect is reset, it can resynchronize to the new timestamp value. The clock must not be stopped to any part of the timestamp interconnect without a reset when the clock restarts, because it does not otherwise resynchronize to the correct timestamp.

Only the timestamp generator is programmable. The other components have no programmers model and operate autonomously.

See Chapter 2 Functional Overview for more information about block diagrams and key features.