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Home > Programmers Model > DAP register descriptions > AXI-AP registers descriptions |
This section describes the following AXI-AP registers:
Configures and controls transfers through the AXI interface.
See DAP register summary.
Figure 3.201 shows the bit assignments.
Table 3.220 shows the bit assignments.
Table 3.220. AXI-AP CSW register bit assignments
Bits | Type | Name | Reset value | Function |
---|---|---|---|---|
[31] | - | Reserved | - | - |
[30:28] | RW | Prot | 0b011 | Specifies protection encoding as AMBA AXI protocol describes. |
[27:24] | RW | Cache | 0b0000 | Specifies the cache encoding as AMBA AXI protocol describes. |
[23] | RO | SPIStatus | - | Indicates the status of the spiden port. If SPIStatus is LOW, then no secure AXI transfers are carried out. |
[22:15] | - | Reserved | - | - |
[14:13] | RW | Domain | 0b11 | Shareable transaction encoding for ACE.
NoteIn revisions of AXI-AP prior to r0p3, this field was reset
to |
[12] | RW | ACEEnable | 0b0 | Enable ACE transactions, including barriers.
|
[11:8] | RW | Mode | 0b0000 | Specifies the mode of operation:
|
[7] | RO | TrInProg | - | Transfer in progress. This field indicates whether a transfer is currently in progress on the AXI master port. |
[6] | RO | DbgStatus | Indicates the status of DBGEN port. If DbgStatus is LOW, then no AXI transfers are carried out.
| |
[5:4] | RW | AddrInc | 0b00 | Auto address increment and packing mode on RW data access. Only increments if the current transaction completes without an Error response and the transaction is not aborted. Auto
address incrementing and packed data transfers are not performed
on access to banked data registers The following values represent the increments and wraps within a 1K address boundary:
The size of address increment is defined by the Size field. |
[3] | - | Reserved | - | |
[2:0] | RW | Size | 0b010 | Size of the data access to perform.
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Defines the current address of the transfer.
For a 32-bit address, this contains the entire address value.
For an LPAE, this contains only the lower 32 bits of the address.
See DAP register summary.
Figure 3.202 shows the bit assignments.
Table 3.221 shows the bit assignments.
Table 3.221. AXI-AP Transfer Address register bit assignments
Bits | Type | Name | Reset value | Function |
---|---|---|---|---|
[63:32] | RW | Address | 0x00000000 | Address of the current transfer. |
[31:0] | RW | Address | 0x00000000 | Address of the current transfer. |
Stores the read data to be read for a read transfer. For a write transfer, write data must be written in the register.
See DAP register summary.
Figure 3.203 shows the bit assignments.
Table 3.222 shows the bit assignments.
Table 3.222. AXI-AP Data RW register bit assignments
Bits | Type | Name | Function |
---|---|---|---|
[31:0] | RW | Data | For 32-bit data access on the AXI-interface, store or write the 32 bits of data into this register once.
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For 64-bit access, multiple accesses must be initiated to DRW to make a single AXI access.
The first read of DRW in a sequence initiates a memory access. The first read returns the lower 32 bits of data. Subsequent read access returns the upper 32 bits of data. If a write to the CSW or TAR is initiated before the sequence completes, then the read access is terminated, and read data is no longer available.
The first write to DRW specifies the lower 32 bits of data to be written. Subsequent write access specifies the upper 32 bits to be written. If a write to the CSW is initiated before the sequence completes, then the write access is not initiated on the AXI interface.
Combining partial reads and writes in a sequence terminates the earlier access. Also, the latest access is not recognized.
Any write access to the CSW register, TAR, or to any other register in the AP during a sequence terminates the ongoing access. Also, the current access is not recognized.
If a write sequence is terminated, then there is no write on the AXI interface.
BD0-3 provide a mechanism for direct mapping through DAP accesses to AXI transfers without having to rewrite the TAR within a 4-location boundary. For example, BD0 reads and writes from TAR. BD1 reads and writes from TAR+4. This is applicable for a 32-bit access.
See DAP register summary.
Figure 3.204 shows the bit assignments.
Table 3.223 shows the bit assignments.
Table 3.223. AXI-AP Banked Data registers bit assignments
Bits | Type | Name | Function |
---|---|---|---|
[31:0] | RW | Data | If dapcaddr[7:4] =
Auto address incrementing is not performed on DAP accesses to BD0-BD3. Banked transfers are only supported for word transfers for 32-bit data. Non-word banked transfers are reserved and unpredictable. Transfer size is ignored for banked transfers. |
Enables or disables the ACE barrier transactions.
See DAP register summary.
Figure 3.205 shows the bit assignments.
Table 3.224 shows the bit assignments.
Table 3.224. ACE Barrier Transaction register bit assignments
Bits | Type | Name | Reset value | Function |
---|---|---|---|---|
[31:3] | - | Reserved | - | |
[2:1] | RW | BarTran | 0b00 | Barrier transactions.
|
[0] | RW | TrgBarTran | 0b0 | The possible values are:
|
Provides an index into the connected memory-mapped resource. It points to one of these resources:
The start of a set of debug registers.
The ROM table that describes the connected debug component.
When the long address extension is implemented, the Debug Base Address Register is:
A 64-bit register.
Split between offsets 0xF0
and 0xF8
in
the register space.
The third register in the last register bank 0xF
:
BASE[63:32] are at offset 0xF0
.
BASE[31:0] are at offset 0xF8
.
See DAP register summary.
Figure 3.206 shows the bit assignments for BASE[63:32].
Table 3.225 shows the bit assignments for BASE[63:32].
Table 3.225. AXI-AP Debug Base Address register, BASE[63:32] bit assignments
Bits | Type | Name | Function |
---|---|---|---|
[63:32] | RO | Debug Base Address bits [63:32] | Base address of either debug ROM table or start of a set of debug registers. The ROM table provides a look-up table for system components. The base address is set to the tie-off value on the static input port, rombaseaddru[31:0]. |
Figure 3.207 shows the bit assignments for BASE[31:0].
Table 3.226 shows the bit assignments for BASE[31:0].
Table 3.226. AXI-AP Debug Base Address register, BASE[31:0] bit assignments
Bits | Type | Name | Function |
---|---|---|---|
[31:0] | RO | Debug Base Address bits [31:0] | Base address of either debug ROM table or start of a set of debug registers. The ROM table provides a look-up table for system components. Bit[1] is always 1, and the other bits are set to the tie-off value on the static input port, rombaseaddrl[31:0]. Set bit[0] to 1 if there are debug components on this bus. |
Provides information about the revision.
See DAP register summary.
Figure 3.208 shows the bit assignments.
Table 3.227 shows the bit assignments.
Table 3.227. AXI-AP Configuration register bit assignments
Bits | Type | Name | Function |
---|---|---|---|
[31:3] | - | Reserved | - |
[2] | RO | LD | Large data. Indicates support for data items larger then 32 bits.
|
[1] | RO | LA | Long address. Indicates support for greater than 32 bits of addressing.
|
[0] | RO | BE | Big-endian. Always read as 0, because AXI-AP supports little-endian. |
Provides information about revision.
See DAP register summary.
Figure 3.209 shows the bit assignments.
Table 3.228 shows bit assignments.
Table 3.228. AXI-AP Identification Register bit assignments
Bits | Type | Name | Reset value | Function |
---|---|---|---|---|
[31:28] | RO | Revision | 0x3 | r1p0. |
[27:24] | RO | JEDEC Bank | 0x4 | Designed by ARM. |
[23:17] | RO | JEDEC Code | 0x3B | Designed by ARM. |
[16] | RO | Mem AP | 0x1 | Mem AP. |
[15:8] | - | Reserved | 0x00 | - |
[7:0] | RO | Identity value | 0x04 | AXI-AP. |