ARM CoreSight SoC-400 Technical Reference Manual: 3.17.3. AXI-AP registers descriptions

3.17.3. AXI-AP registers descriptions

This section describes the following AXI-AP registers:

AXI-AP Control/Status Word register

Purpose: Configures and controls transfers through the AXI interface.
Attributes: See DAP register summary.

Figure 3.201 shows the bit assignments.

Figure 3.201. AXI-AP CSW register bit assignments

Table 3.220 shows the bit assignments.

Table 3.220. AXI-AP CSW register bit assignments

Bits	Type	Name	Reset value	Function
[31]	-	Reserved	-	-
[30:28]	RW	Prot	`0b011`	Specifies protection encoding as AMBA AXI protocol describes.
[27:24]	RW	Cache	`0b0000`	Specifies the cache encoding as AMBA AXI protocol describes.
[23]	RO	SPIStatus	-	Indicates the status of the spiden port. If SPIStatus is LOW, then no secure AXI transfers are carried out.
[22:15]	-	Reserved	-	-
[14:13]	RW	Domain	`0b11`	Shareable transaction encoding for ACE. `0b00` Non shareable. `0b01` Shareable, inner domain, includes additional masters. `0b10` Shareable, outer domain, also includes inner or additional masters. `0b11` Shareable, system domain, all masters included. Note In revisions of AXI-AP prior to r0p3, this field was reset to `0b00`. ARM recommends that you set this field to a valid value before issuing any AXI transactions, for compatibility with revisions prior to r0p3.
[12]	RW	ACEEnable	`0b0`	Enable ACE transactions, including barriers. `0` Disable. `1` Enable.
[11:8]	RW	Mode	`0b0000`	Specifies the mode of operation: `0b0000` Normal download or upload. `0b0001` Barrier transaction. `0b0010`-`0b1111` Reserved, SBZ.
[7]	RO	TrInProg	-	Transfer in progress. This field indicates whether a transfer is currently in progress on the AXI master port.
[6]	RO	DbgStatus		Indicates the status of DBGEN port. If DbgStatus is LOW, then no AXI transfers are carried out. `0` AXI transactions are stopped. `1` AXI transactions are permitted.
[5:4]	RW	AddrInc	`0b00`	Auto address increment and packing mode on RW data access. Only increments if the current transaction completes without an Error response and the transaction is not aborted. Auto address incrementing and packed data transfers are not performed on access to banked data registers `0x10`-`0x1C`. The status of these bits is ignored in these cases. The following values represent the increments and wraps within a 1K address boundary: `0b00` Auto increment OFF. `0b01` Single increment. Single transfer from byte lane. `0b10` Increment packed. Word Same effect as single increment. Byte or Halfword Packs of four 8-bit transfers or two 16-bit transfers into a 32-bit DAP transfer. `0b11` Reserved, no transfer. The size of address increment is defined by the Size field.
[3]	-	Reserved		-
[2:0]	RW	Size	`0b010`	Size of the data access to perform. `0b000` 8-bit. `0b001` 16-bit. `0b010` 32-bit. `0b011` 64-bit. `0b100`-`0b111` Reserved, SBZ.

AXI-AP Transfer Address Register

Purpose

Defines the current address of the transfer.

For a 32-bit address, this contains the entire address value.
For an LPAE, this contains only the lower 32 bits of the address.

Attributes

See DAP register summary.

Figure 3.202 shows the bit assignments.

Figure 3.202. AXI-AP Transfer Address register bit assignments

Table 3.221 shows the bit assignments.

Table 3.221. AXI-AP Transfer Address register bit assignments

Bits	Type	Name	Reset value	Function
[63:32]	RW	Address	`0x00000000`	Address of the current transfer.
[31:0]	RW	Address	`0x00000000`	Address of the current transfer.

AXI-AP Data RW register

Purpose: Stores the read data to be read for a read transfer. For a write transfer, write data must be written in the register.
Attributes: See DAP register summary.

Figure 3.203 shows the bit assignments.

Figure 3.203. AXI-AP Data RW register bit assignments

Table 3.222 shows the bit assignments.

Table 3.222. AXI-AP Data RW register bit assignments

Bits	Type	Name	Function
[31:0]	RW	Data	For 32-bit data access on the AXI-interface, store or write the 32 bits of data into this register once. Read mode Data value read from the current transfer. Write mode Data value to write for the current transfer.

Note

For 64-bit access, multiple accesses must be initiated to DRW to make a single AXI access.

Read

The first read of DRW in a sequence initiates a memory access. The first read returns the lower 32 bits of data. Subsequent read access returns the upper 32 bits of data. If a write to the CSW or TAR is initiated before the sequence completes, then the read access is terminated, and read data is no longer available.

Write

The first write to DRW specifies the lower 32 bits of data to be written. Subsequent write access specifies the upper 32 bits to be written. If a write to the CSW is initiated before the sequence completes, then the write access is not initiated on the AXI interface.

Combining partial reads and writes in a sequence terminates the earlier access. Also, the latest access is not recognized.
Any write access to the CSW register, TAR, or to any other register in the AP during a sequence terminates the ongoing access. Also, the current access is not recognized.
If a write sequence is terminated, then there is no write on the AXI interface.

AXI-AP Banked Data registers

Purpose: BD0-3 provide a mechanism for direct mapping through DAP accesses to AXI transfers without having to rewrite the TAR within a 4-location boundary. For example, BD0 reads and writes from TAR. BD1 reads and writes from TAR+4. This is applicable for a 32-bit access.
Attributes: See DAP register summary.

Figure 3.204 shows the bit assignments.

Figure 3.204. AXI-AP Banked DATA register bit assignments

Table 3.223 shows the bit assignments.

Table 3.223. AXI-AP Banked Data registers bit assignments

Bits Type Name Function

[31:0]

Data

Bits	Type	Name	Function
[31:0]	RW	Data	If dapcaddr[7:4] = `0x0001`, it is accessing AXI-AP registers in the range `0x10`-`0x1C`, and the derived `ADDR[ADDR_WIDTH-1:0]` in RW, 32-bit mode is as follows: For a 32-bit address mode, the external address is TAR[31:4] + DAPADDR[3:2] + `0b00`. For the LPAE mode, the external address is TAR[63:4] + DAPADDR[3:2] + `0b00`. Auto address incrementing is not performed on DAP accesses to BD0-BD3. Banked transfers are only supported for word transfers for 32-bit data. Non-word banked transfers are reserved and unpredictable. Transfer size is ignored for banked transfers.

If dapcaddr[7:4] = 0x0001, it is accessing AXI-AP registers in the range 0x10-0x1C, and the derived ADDR[ADDR_WIDTH-1:0] in RW, 32-bit mode is as follows:

For a 32-bit address mode, the external address is TAR[31:4] + DAPADDR[3:2] + 0b00.
For the LPAE mode, the external address is TAR[63:4] + DAPADDR[3:2] + 0b00.

Auto address incrementing is not performed on DAP accesses to BD0-BD3.

Banked transfers are only supported for word transfers for 32-bit data. Non-word banked transfers are reserved and unpredictable. Transfer size is ignored for banked transfers.

AXI-AP ACE Barrier Transaction register

Purpose: Enables or disables the ACE barrier transactions.
Attributes: See DAP register summary.

Figure 3.205 shows the bit assignments.

Figure 3.205. ACE Barrier Transaction register bit assignments

Table 3.224 shows the bit assignments.

Table 3.224. ACE Barrier Transaction register bit assignments

Bits	Type	Name	Reset value	Function
[31:3]	-	Reserved		-
[2:1]	RW	BarTran	`0b00`	Barrier transactions. `0b00` Barrier with normal access. `0b01` Memory barrier. `0b10` Reserved. `0b11` Synchronization barrier.
[0]	RW	TrgBarTran	`0b0`	The possible values are: 0 Disable barrier transaction. 1 Enable barrier transaction.

AXI-AP Debug Base Address register

Purpose

Provides an index into the connected memory-mapped resource. It points to one of these resources:

The start of a set of debug registers.
The ROM table that describes the connected debug component.

When the long address extension is implemented, the Debug Base Address Register is:

A 64-bit register.
Split between offsets 0xF0 and 0xF8 in the register space.
The third register in the last register bank 0xF:
- BASE[63:32] are at offset 0xF0.
- BASE[31:0] are at offset 0xF8.

Attributes

See DAP register summary.

AXI-AP Debug Base Address register, BASE [63:32]

Figure 3.206 shows the bit assignments for BASE[63:32].

Figure 3.206. AXI-AP Debug Base Address register, BASE[63:32] bit assignments

Table 3.225 shows the bit assignments for BASE[63:32].

Table 3.225. AXI-AP Debug Base Address register, BASE[63:32] bit assignments

Bits	Type	Name	Function
[63:32]	RO	Debug Base Address bits [63:32]	Base address of either debug ROM table or start of a set of debug registers. The ROM table provides a look-up table for system components. The base address is set to the tie-off value on the static input port, rombaseaddru[31:0].

Bits

Type

Name

Function

[63:32]

Debug Base Address bits [63:32]

Base address of either debug ROM table or start of a set of debug registers. The ROM table provides a look-up table for system components.

The base address is set to the tie-off value on the static input port, rombaseaddru[31:0].

AXI-AP Debug Base Address register, BASE [31:0]

Figure 3.207 shows the bit assignments for BASE[31:0].

Figure 3.207. AXI-AP Debug Base Address register, BASE[31:0] bit assignments

Table 3.226 shows the bit assignments for BASE[31:0].

Table 3.226. AXI-AP Debug Base Address register, BASE[31:0] bit assignments

Bits	Type	Name	Function
[31:0]	RO	Debug Base Address bits [31:0]	Base address of either debug ROM table or start of a set of debug registers. The ROM table provides a look-up table for system components. Bit[1] is always 1, and the other bits are set to the tie-off value on the static input port, rombaseaddrl[31:0]. Set bit[0] to 1 if there are debug components on this bus.

Bits

Type

Name

Function

[31:0]

Debug Base Address bits [31:0]

Base address of either debug ROM table or start of a set of debug registers. The ROM table provides a look-up table for system components.

Bit[1] is always 1, and the other bits are set to the tie-off value on the static input port, rombaseaddrl[31:0].

Set bit[0] to 1 if there are debug components on this bus.

AXI-AP Configuration register

Purpose: Provides information about the revision.
Attributes: See DAP register summary.

Figure 3.208 shows the bit assignments.

Figure 3.208. AXI-AP Configuration register bit assignments

Table 3.227 shows the bit assignments.

Table 3.227. AXI-AP Configuration register bit assignments

Bits	Type	Name	Function
[31:3]	-	Reserved	-
[2]	RO	LD	Large data. Indicates support for data items larger then 32 bits. 0 Only 8, 16, 32-bit data items are supported. 1 Support for 64-bit data item in addition to 8, 16, 32-bit data.
[1]	RO	LA	Long address. Indicates support for greater than 32 bits of addressing. 0 32 or fewer bits of addressing. Registers `0x08` and `0xF0` are reserved. 1 64 or fewer bits of addressing. TAR.l and DBAR.l occupy two locations, at `0x04` and `0x08`, and at `0xF8` and `0xF0` respectively.
[0]	RO	BE	Big-endian. Always read as 0, because AXI-AP supports little-endian.

AXI-AP Identification Register, IDR

Purpose: Provides information about revision.
Attributes: See DAP register summary.

Figure 3.209 shows the bit assignments.

Figure 3.209. AXI-AP Identification Register bit assignments

Table 3.228 shows bit assignments.

Table 3.228. AXI-AP Identification Register bit assignments

Bits	Type	Name	Reset value	Function
[31:28]	RO	Revision	`0x3`	r1p0.
[27:24]	RO	JEDEC Bank	`0x4`	Designed by ARM.
[23:17]	RO	JEDEC Code	`0x3B`	Designed by ARM.
[16]	RO	Mem AP	`0x1`	Mem AP.
[15:8]	-	Reserved	`0x00`	-
[7:0]	RO	Identity value	`0x04`	AXI-AP.

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