A.3.2. ATB trace funnel signals

Table A.15 shows the ATB trace funnel signals.

Table A.15. ATB trace funnel signals

NameTypeClock domainDescription
afreadys<x>[a]InputclkATB data flush complete for the slave port <x>.
afvalidm InputclkATB data flush request for the master port.
atbytess<x>[<bw>:0][a][b]InputclkATB number of valid bytes, LSB aligned, on the slave port <x>.
clkInputclkATB clock.
atdatas<x>[<dw>:0] [a][c]InputclkATB trace data on the slave port <x>.
atids<x>[6:0] [a]InputclkATB ID for current trace data on slave port <x>.
atreadym InputclkATB transfer ready on master port.
resetnInputclkATB reset.
atvalids<x>[a]InputclkATB valid signal present on slave port <x>.
paddrdbg[11:2] InputclkDebug APB address bus.
paddrdbg31 InputclkEnables components to distinguish between internal accesses from system software, and external accesses from a debugger.
pclkendbgInputclkDebug APB clock enable.
penabledbg InputclkDebug APB enable signal, indicates second and subsequent cycles.
pseldbg InputclkDebug APB component select.
pwdatadbg[31:0] InputclkDebug APB write data bus.
pwritedbg InputclkDebug APB write transfer.
syncreqmInputclkSynchronization request.
afreadym OutputclkATB data flush complete for the master port.
afvalids<x>[a]OutputclkATB data flush request for the slave port <x>.
atbytesm[<bw>:0][b]OutputclkATB number of valid bytes, LSB aligned, on the master port.
atdatam[<dw>:0][c]OutputclkATB trace data on the master port.
atidm[6:0] OutputclkATB ID for current trace data on master port.
atreadys<x>[a]OutputclkATB transfer ready on slave port <x>.
atvalidm OutputclkATB valid signals present on master port.
prdatadbg[31:0] OutputclkDebug APB read data bus.
preadydbg OutputclkDebug APB ready signal.
syncreqs<x>[a]OutputclkSynchronization request.

[a] Where the value of <x> can be 0-7.

[b] Where <bw> is in the range 0-3 and is automatically calculated at configuration time.

[c] Where <dw> is the data width of the interface minus one.

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