3.4. APB interconnect register summary

Table 3.22 shows the APB interconnect registers in offset order from the base memory address.

Table 3.22. APB interconnect register summary

Offset

Name

Type

Reset

Description

0x000-0x0FC

ROM_ENTRY_n[a]

RO

-[b]

ROM Table Entry

0xFD0

PIDR4

RO

unknown[c]

Peripheral ID4 Register

0xFD4

-

-

-

Reserved

0xFD8

-

-

-

Reserved

0xFDC

-

-

-

Reserved

0xFE0

PIDR0

RO

-[d]

Peripheral ID0 Register

0xFE4

PIDR1

RO

unknown[e]

Peripheral ID1 Register

0xFE8

PIDR2

RO

unknown[f]

Peripheral ID2 Register

0xFEC

PIDR3

RO

0x00000000

Peripheral ID3 Register

0xFF0

CIDR0

RO

0x0000000D

Component ID0 Register

0xFF4

CIDR1

RO

0x00000010

Component ID1 Register

0xFF8

CIDR2

RO

0x00000005

Component ID2 Register

0xFFC

CIDR3

RO

0x000000B1

Component ID3 Register

[a] Where n is 0-63.

[b] The reset value depends on the value of the MASTER_INTFn_BASE_ADDR parameter, where n is 0-63. See Additional reading.

[c] See Table 3.24 for information on the reset value and its dependencies.

[d] The reset value depends on the system configuration, and identifies this as either a generic ROM table or a top-level ROM table.

[e] See Table 3.26 for information on the reset value and its dependencies.

[f] See Table 3.27 for information on the reset value and its dependencies.


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