A.3.6. ATB synchronous bridge signals

Table A.20 shows the ATB synchronous bridge signals.

Table A.20. ATB synchronous bridge signals

NameTypeClock domainDescription
afreadysInputclkATB data flush complete.
afvalidmInputclkATB data flush request.
atbytess[<bw>:0][a]InputclkATB number of valid bytes, LSB aligned, on the slave port.
clkInputclkATB clock.
clkensInputclkATB clock enable.
clkenmInputclkATB clock enable.
atdatas[<dw>:0][b]InputclkATB trace data.
atids[6:0]InputclkATB ID for the present trace data.
atreadymInputclkATB transfer ready.
resetnInputclkATB reset for the ATCLK domain.
atvalidsInputclkATB valid signal present.
csysreq[c]InputclkClock powerdown request.
syncreqmInputclkSynchronization request.
afreadymOutputclkATB data flush complete.
afvalidsOutputclkATB data flush request.
atbytesm[<bw>:0][b]OutputclkATB number of valid bytes, LSB aligned, on the master port.
atdatam[<dw>:0][b]OutputclkATB trace data.
atidmOutputclkATB ID for current trace data.
atreadysOutputclkATB transfer ready.
atvalidmOutputclkATB valid signals present.
cactive[c]OutputclkClock is required when driven HIGH.
csysack[c]OutputclkClock powerdown acknowledge.
syncreqsOutputclkSynchronization request.

[a] <bw> has a range of 0-3.

[b] <dw> is the data width of the interface, minus one.

[c] This signal is only present if you configure the device to have an LPI.

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